Subversion Repositories simple_fm_receiver

-- ------------------------------------------------------------------------

-- Copyright (C) 2004 Arif Endro Nugroho

-- All rights reserved.

-- 

-- Redistribution and use in source and binary forms, with or without

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-- 1. Redistributions of source code must retain the above copyright

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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS

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-- ------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity addacc is

   port (

    clock  : in  bit;

    acc    : in  bit_vector (17 downto 0);

    result : out bit_vector (17 downto 0);

    offset : in  bit_vector (17 downto 0)

    );

end addacc;

architecture structural of addacc is

   component adder_18bit

      port (

      addend_18bit   : in  bit_vector (17 downto 0);

      augend_18bit   : in  bit_vector (17 downto 0);

      adder18_output : out bit_vector (17 downto 0)

      );

   end component;

signal result_adder01     : bit_vector (17 downto 0);

signal result_adder02     : bit_vector (17 downto 0);

signal result_adder02_reg : bit_vector (17 downto 0);

begin

adder01 : adder_18bit

  port map (

  addend_18bit     => offset,

  augend_18bit     => acc,

  adder18_output   => result_adder01

  );

adder02 : adder_18bit

  port map (

  addend_18bit     => result_adder01,

  augend_18bit     => result_adder02_reg,

  adder18_output   => result_adder02

  );

  process (clock)

  begin

          if ((clock = '1') and clock'event) then

                  result_adder02_reg <= result_adder02;

                  result <= result_adder02;

          end if;

  end process;

end structural;