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-- $Id: adder_16bit.vhdl,v 1.4 2008-06-26 06:12:29 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title       : Adder 16 bit
-- Project     : FM Receiver 
-------------------------------------------------------------------------------
-- File        : adder_16bit.vhdl
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created     : 2004/12/23
-- Last update : 
-- Simulators  : 
-- Synthesizers: 
-- Target      : 
-------------------------------------------------------------------------------
-- Description : Ripple carry adder 16 bit with output 17 bit
-------------------------------------------------------------------------------
-- Copyright (C) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- 
--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
-- 
-------------------------------------------------------------------------------
-- 
--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity adder_16bit is
   port (
      addend_16bit  : in  bit_vector (15 downto 0);
      augend_16bit  : in  bit_vector (15 downto 0);
      adder16_output: out bit_vector (16 downto 0) -- 17 bit output
      );
end adder_16bit;
 
architecture structural of adder_16bit is
 
   component fulladder
      port (
      addend        : in   bit;
      augend        : in   bit;
      carry_in      : in   bit;
      sum           : out  bit;
      carry         : out  bit
      );
   end component;
 
-- internal signal
signal c00 : bit;
signal c01 : bit;
signal c02 : bit;
signal c03 : bit;
signal c04 : bit;
signal c05 : bit;
signal c06 : bit;
signal c07 : bit;
signal c08 : bit;
signal c09 : bit;
signal c10 : bit;
signal c11 : bit;
signal c12 : bit;
signal c13 : bit;
signal c14 : bit;
signal c15 : bit;
signal c16 : bit;
signal over16 : bit;
signal adder16_output_int : bit_vector (15 downto 0);
signal ov  : bit;
 
begin
 
c00                     <= '0';
over16                  <= (addend_16bit (15) xor augend_16bit (15));
ov                      <= ((adder16_output_int (15) and over16) or
                           (c16 and (not (over16))));
adder16_output(15 downto 00) <= adder16_output_int;
adder16_output(16)           <= ov;
 
fa15 : fulladder
   port map (
      addend     => addend_16bit(15),
      augend     => augend_16bit(15),
      carry_in   => c15,
      sum        => adder16_output_int(15),
      carry      => c16
      );
 
fa14 : fulladder
   port map (
      addend     => addend_16bit(14),
      augend     => augend_16bit(14),
      carry_in   => c14,
      sum        => adder16_output_int(14),
      carry      => c15
      );
 
fa13 : fulladder
   port map (
      addend     => addend_16bit(13),
      augend     => augend_16bit(13),
      carry_in   => c13,
      sum        => adder16_output_int(13),
      carry      => c14
      );
 
fa12 : fulladder
   port map (
      addend     => addend_16bit(12),
      augend     => augend_16bit(12),
      carry_in   => c12,
      sum        => adder16_output_int(12),
      carry      => c13
      );
 
fa11 : fulladder
   port map (
      addend     => addend_16bit(11),
      augend     => augend_16bit(11),
      carry_in   => c11,
      sum        => adder16_output_int(11),
      carry      => c12
      );
 
fa10 : fulladder
   port map (
      addend     => addend_16bit(10),
      augend     => augend_16bit(10),
      carry_in   => c10,
      sum        => adder16_output_int(10),
      carry      => c11
      );
 
fa09 : fulladder
   port map (
      addend     => addend_16bit(09),
      augend     => augend_16bit(09),
      carry_in   => c09,
      sum        => adder16_output_int(09),
      carry      => c10
      );
 
fa08 : fulladder
   port map (
      addend     => addend_16bit(08),
      augend     => augend_16bit(08),
      carry_in   => c08,
      sum        => adder16_output_int(08),
      carry      => c09
      );
 
fa07 : fulladder
   port map (
      addend     => addend_16bit(07),
      augend     => augend_16bit(07),
      carry_in   => c07,
      sum        => adder16_output_int(07),
      carry      => c08
      );
 
fa06 : fulladder
   port map (
      addend     => addend_16bit(06),
      augend     => augend_16bit(06),
      carry_in   => c06,
      sum        => adder16_output_int(06),
      carry      => c07
      );
 
fa05 : fulladder
   port map (
      addend     => addend_16bit(05),
      augend     => augend_16bit(05),
      carry_in   => c05,
      sum        => adder16_output_int(05),
      carry      => c06
      );
 
fa04 : fulladder
   port map (
      addend     => addend_16bit(04),
      augend     => augend_16bit(04),
      carry_in   => c04,
      sum        => adder16_output_int(04),
      carry      => c05
      );
 
fa03 : fulladder
   port map (
      addend     => addend_16bit(03),
      augend     => augend_16bit(03),
      carry_in   => c03,
      sum        => adder16_output_int(03),
      carry      => c04
      );
 
fa02 : fulladder
   port map (
      addend     => addend_16bit(02),
      augend     => augend_16bit(02),
      carry_in   => c02,
      sum        => adder16_output_int(02),
      carry      => c03
      );
 
fa01 : fulladder
   port map (
      addend     => addend_16bit(01),
      augend     => augend_16bit(01),
      carry_in   => c01,
      sum        => adder16_output_int(01),
      carry      => c02
      );
 
fa00 : fulladder
   port map (
      addend     => addend_16bit(00),
      augend     => augend_16bit(00),
      carry_in   => c00,
      sum        => adder16_output_int(00),
      carry      => c01
      );
 
end structural;

Line No.	Rev	Author	Line
1	22	arif_endro	`-- $Id: adder_16bit.vhdl,v 1.4 2008-06-26 06:12:29 arif_endro Exp $`
2	2	arif_endro	`-------------------------------------------------------------------------------`
3			`-- Title : Adder 16 bit`
4			`-- Project : FM Receiver`
5			`-------------------------------------------------------------------------------`
6			`-- File : adder_16bit.vhdl`
7			`-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>`
8			`-- Created : 2004/12/23`
9			`-- Last update :`
10	13	arif_endro	`-- Simulators :`
11	2	arif_endro	`-- Synthesizers:`
12			`-- Target :`
13			`-------------------------------------------------------------------------------`
14			`-- Description : Ripple carry adder 16 bit with output 17 bit`
15			`-------------------------------------------------------------------------------`
16	13	arif_endro	`-- Copyright (C) 2004 Arif E. Nugroho`
17	2	arif_endro	`-- This VHDL design file is an open design; you can redistribute it and/or`
18			`-- modify it and/or implement it after contacting the author`
19			`-------------------------------------------------------------------------------`
20	13	arif_endro	`-------------------------------------------------------------------------------`
21			`--`
22			`-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION`
23			`-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT`
24			`-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE`
25			`-- ASSOCIATED DISCLAIMER.`
26			`--`
27			`-------------------------------------------------------------------------------`
28			`--`
29			-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30			`-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF`
31			`-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO`
32			`-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,`
33			`-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
34			`-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;`
35			`-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,`
36			`-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR`
37			`-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
38			`-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
39			`--`
40			`-------------------------------------------------------------------------------`
41	2	arif_endro
42			`library IEEE;`
43			`use IEEE.STD_LOGIC_1164.ALL;`
44
45			`entity adder_16bit is`
46			`port (`
47			`addend_16bit : in bit_vector (15 downto 0);`
48			`augend_16bit : in bit_vector (15 downto 0);`
49			`adder16_output: out bit_vector (16 downto 0) -- 17 bit output`
50			`);`
51			`end adder_16bit;`
52
53			`architecture structural of adder_16bit is`
54
55			`component fulladder`
56			`port (`
57			`addend : in bit;`
58			`augend : in bit;`
59			`carry_in : in bit;`
60			`sum : out bit;`
61			`carry : out bit`
62			`);`
63			`end component;`
64
65			`-- internal signal`
66			`signal c00 : bit;`
67			`signal c01 : bit;`
68			`signal c02 : bit;`
69			`signal c03 : bit;`
70			`signal c04 : bit;`
71			`signal c05 : bit;`
72			`signal c06 : bit;`
73			`signal c07 : bit;`
74			`signal c08 : bit;`
75			`signal c09 : bit;`
76			`signal c10 : bit;`
77			`signal c11 : bit;`
78			`signal c12 : bit;`
79			`signal c13 : bit;`
80			`signal c14 : bit;`
81			`signal c15 : bit;`
82			`signal c16 : bit;`
83			`signal over16 : bit;`
84	22	arif_endro	`signal adder16_output_int : bit_vector (15 downto 0);`
85			`signal ov : bit;`
86	2	arif_endro
87			`begin`
88
89			`c00 <= '0';`
90			`over16 <= (addend_16bit (15) xor augend_16bit (15));`
91	22	arif_endro	`ov <= ((adder16_output_int (15) and over16) or`
92	2	arif_endro	`(c16 and (not (over16))));`
93	22	arif_endro	`adder16_output(15 downto 00) <= adder16_output_int;`
94			`adder16_output(16) <= ov;`
95	2	arif_endro
96			`fa15 : fulladder`
97			`port map (`
98			`addend => addend_16bit(15),`
99			`augend => augend_16bit(15),`
100			`carry_in => c15,`
101			`sum => adder16_output_int(15),`
102			`carry => c16`
103			`);`
104
105			`fa14 : fulladder`
106			`port map (`
107			`addend => addend_16bit(14),`
108			`augend => augend_16bit(14),`
109			`carry_in => c14,`
110			`sum => adder16_output_int(14),`
111			`carry => c15`
112			`);`
113
114			`fa13 : fulladder`
115			`port map (`
116			`addend => addend_16bit(13),`
117			`augend => augend_16bit(13),`
118			`carry_in => c13,`
119			`sum => adder16_output_int(13),`
120			`carry => c14`
121			`);`
122
123			`fa12 : fulladder`
124			`port map (`
125			`addend => addend_16bit(12),`
126			`augend => augend_16bit(12),`
127			`carry_in => c12,`
128			`sum => adder16_output_int(12),`
129			`carry => c13`
130			`);`
131
132			`fa11 : fulladder`
133			`port map (`
134			`addend => addend_16bit(11),`
135			`augend => augend_16bit(11),`
136			`carry_in => c11,`
137			`sum => adder16_output_int(11),`
138			`carry => c12`
139			`);`
140
141			`fa10 : fulladder`
142			`port map (`
143			`addend => addend_16bit(10),`
144			`augend => augend_16bit(10),`
145			`carry_in => c10,`
146			`sum => adder16_output_int(10),`
147			`carry => c11`
148			`);`
149
150			`fa09 : fulladder`
151			`port map (`
152			`addend => addend_16bit(09),`
153			`augend => augend_16bit(09),`
154			`carry_in => c09,`
155			`sum => adder16_output_int(09),`
156			`carry => c10`
157			`);`
158
159			`fa08 : fulladder`
160			`port map (`
161			`addend => addend_16bit(08),`
162			`augend => augend_16bit(08),`
163			`carry_in => c08,`
164			`sum => adder16_output_int(08),`
165			`carry => c09`
166			`);`
167
168			`fa07 : fulladder`
169			`port map (`
170			`addend => addend_16bit(07),`
171			`augend => augend_16bit(07),`
172			`carry_in => c07,`
173			`sum => adder16_output_int(07),`
174			`carry => c08`
175			`);`
176
177			`fa06 : fulladder`
178			`port map (`
179			`addend => addend_16bit(06),`
180			`augend => augend_16bit(06),`
181			`carry_in => c06,`
182			`sum => adder16_output_int(06),`
183			`carry => c07`
184			`);`
185
186			`fa05 : fulladder`
187			`port map (`
188			`addend => addend_16bit(05),`
189			`augend => augend_16bit(05),`
190			`carry_in => c05,`
191			`sum => adder16_output_int(05),`
192			`carry => c06`
193			`);`
194
195			`fa04 : fulladder`
196			`port map (`
197			`addend => addend_16bit(04),`
198			`augend => augend_16bit(04),`
199			`carry_in => c04,`
200			`sum => adder16_output_int(04),`
201			`carry => c05`
202			`);`
203
204			`fa03 : fulladder`
205			`port map (`
206			`addend => addend_16bit(03),`
207			`augend => augend_16bit(03),`
208			`carry_in => c03,`
209			`sum => adder16_output_int(03),`
210			`carry => c04`
211			`);`
212
213			`fa02 : fulladder`
214			`port map (`
215			`addend => addend_16bit(02),`
216			`augend => augend_16bit(02),`
217			`carry_in => c02,`
218			`sum => adder16_output_int(02),`
219			`carry => c03`
220			`);`
221
222			`fa01 : fulladder`
223			`port map (`
224			`addend => addend_16bit(01),`
225			`augend => augend_16bit(01),`
226			`carry_in => c01,`
227			`sum => adder16_output_int(01),`
228			`carry => c02`
229			`);`
230
231			`fa00 : fulladder`
232			`port map (`
233			`addend => addend_16bit(00),`
234			`augend => augend_16bit(00),`
235			`carry_in => c00,`
236			`sum => adder16_output_int(00),`
237			`carry => c01`
238			`);`
239
240			`end structural;`

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[/] [simple_fm_receiver/] [trunk/] [source/] [adder_16bit.vhdl] - Blame information for rev 38