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[/] [simple_fm_receiver/] [trunk/] [source/] [adder_16bit_u.vhdl] - Blame information for rev 39

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1 14 arif_endro 
-- $Id: adder_16bit_u.vhdl,v 1.3 2005-03-04 08:06:17 arif_endro Exp $
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-------------------------------------------------------------------------------
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-- Title       : Adder 16 bit
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-- Project     : FM Receiver
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-------------------------------------------------------------------------------
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-- File        : adder_16bit_u.vhdl
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-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created     : 2004/12/23
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-- Last update :
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-- Simulators  :
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-- Synthesizers:
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-- Target      :
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-------------------------------------------------------------------------------
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-- Description : Ripple carry adder 16 bit with output 16 bit
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-------------------------------------------------------------------------------
16 39 arif_endro 
-- Copyright (C) 2004 Arif Endro Nugroho
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-------------------------------------------------------------------------------
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--
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--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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--
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-------------------------------------------------------------------------------
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--
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--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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--
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-------------------------------------------------------------------------------
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39 
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity adder_16bit_u is
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   port (
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      addend_16bit  : in  bit_vector (15 downto 0);
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      augend_16bit  : in  bit_vector (15 downto 0);
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      adder16_output: out bit_vector (15 downto 0)
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      );
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end adder_16bit_u;
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architecture structural of adder_16bit_u is
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   component fulladder
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      port (
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      addend        : in   bit;
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      augend        : in   bit;
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      carry_in      : in   bit;
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      sum           : out  bit;
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      carry         : out  bit
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      );
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   end component;
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-- internal signal
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signal c00 : bit;
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signal c01 : bit;
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signal c02 : bit;
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signal c03 : bit;
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signal c04 : bit;
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signal c05 : bit;
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signal c06 : bit;
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signal c07 : bit;
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signal c08 : bit;
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signal c09 : bit;
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signal c10 : bit;
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signal c11 : bit;
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signal c12 : bit;
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signal c13 : bit;
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signal c14 : bit;
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signal c15 : bit;
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signal c16 : bit;
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begin
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c00 <= '0';
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fa15 : fulladder
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   port map (
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      addend     => addend_16bit(15),
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      augend     => augend_16bit(15),
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      carry_in   => c15,
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      sum        => adder16_output(15),
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      carry      => c16
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      );
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fa14 : fulladder
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   port map (
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      addend     => addend_16bit(14),
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      augend     => augend_16bit(14),
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      carry_in   => c14,
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      sum        => adder16_output(14),
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      carry      => c15
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      );
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fa13 : fulladder
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   port map (
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      addend     => addend_16bit(13),
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      augend     => augend_16bit(13),
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      carry_in   => c13,
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      sum        => adder16_output(13),
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      carry      => c14
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      );
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fa12 : fulladder
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   port map (
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      addend     => addend_16bit(12),
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      augend     => augend_16bit(12),
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      carry_in   => c12,
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      sum        => adder16_output(12),
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      carry      => c13
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      );
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fa11 : fulladder
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   port map (
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      addend     => addend_16bit(11),
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      augend     => augend_16bit(11),
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      carry_in   => c11,
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      sum        => adder16_output(11),
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      carry      => c12
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      );
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fa10 : fulladder
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   port map (
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      addend     => addend_16bit(10),
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      augend     => augend_16bit(10),
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      carry_in   => c10,
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      sum        => adder16_output(10),
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      carry      => c11
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      );
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fa09 : fulladder
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   port map (
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      addend     => addend_16bit(09),
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      augend     => augend_16bit(09),
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      carry_in   => c09,
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      sum        => adder16_output(09),
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      carry      => c10
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      );
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fa08 : fulladder
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   port map (
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      addend     => addend_16bit(08),
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      augend     => augend_16bit(08),
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      carry_in   => c08,
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      sum        => adder16_output(08),
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      carry      => c09
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      );
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fa07 : fulladder
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   port map (
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      addend     => addend_16bit(07),
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      augend     => augend_16bit(07),
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      carry_in   => c07,
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      sum        => adder16_output(07),
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      carry      => c08
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      );
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fa06 : fulladder
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   port map (
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      addend     => addend_16bit(06),
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      augend     => augend_16bit(06),
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      carry_in   => c06,
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      sum        => adder16_output(06),
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      carry      => c07
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      );
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fa05 : fulladder
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   port map (
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      addend     => addend_16bit(05),
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      augend     => augend_16bit(05),
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      carry_in   => c05,
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      sum        => adder16_output(05),
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      carry      => c06
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      );
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fa04 : fulladder
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   port map (
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      addend     => addend_16bit(04),
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      augend     => augend_16bit(04),
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      carry_in   => c04,
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      sum        => adder16_output(04),
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      carry      => c05
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      );
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fa03 : fulladder
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   port map (
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      addend     => addend_16bit(03),
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      augend     => augend_16bit(03),
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      carry_in   => c03,
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      sum        => adder16_output(03),
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      carry      => c04
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      );
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fa02 : fulladder
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   port map (
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      addend     => addend_16bit(02),
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      augend     => augend_16bit(02),
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      carry_in   => c02,
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      sum        => adder16_output(02),
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      carry      => c03
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      );
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fa01 : fulladder
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   port map (
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      addend     => addend_16bit(01),
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      augend     => augend_16bit(01),
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      carry_in   => c01,
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      sum        => adder16_output(01),
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      carry      => c02
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      );
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fa00 : fulladder
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   port map (
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      addend     => addend_16bit(00),
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      augend     => augend_16bit(00),
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      carry_in   => c00,
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      sum        => adder16_output(00),
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      carry      => c01
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      );
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end structural;

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