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[/] [simple_fm_receiver/] [trunk/] [source/] [adder_18bit.vhdl] - Blame information for rev 36

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-- $Id: adder_18bit.vhdl,v 1.3 2005-03-04 08:06:17 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title       : Adder 18 bit
-- Project     : FM Receiver 
-------------------------------------------------------------------------------
-- File        : adder_18bit.vhdl
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created     : 2004/12/01
-- Last update : 
-- Simulators  : 
-- Synthesizers: 
-- Target      : 
-------------------------------------------------------------------------------
-- Description : Ripple carry adder 18 bit with output 18 bit
-------------------------------------------------------------------------------
-- Copyright (C) 2004 Arif E. Nugroho
-- This VHDL design file is an open design; you can redistribute it and/or
-- modify it and/or implement it after contacting the author
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- 
--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
-- 
-------------------------------------------------------------------------------
-- 
--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity adder_18bit is
   port (
      addend_18bit  : in  bit_vector (17 downto 0);
      augend_18bit  : in  bit_vector (17 downto 0);
      adder18_output: out bit_vector (17 downto 0)
      );
end adder_18bit;
 
architecture structural of adder_18bit is
 
   component fulladder
      port (
      addend        : in   bit;
      augend        : in   bit;
      carry_in      : in   bit;
      sum           : out  bit;
      carry         : out  bit
      );
   end component;
 
-- internal signal
signal c00 : bit;
signal c01 : bit;
signal c02 : bit;
signal c03 : bit;
signal c04 : bit;
signal c05 : bit;
signal c06 : bit;
signal c07 : bit;
signal c08 : bit;
signal c09 : bit;
signal c10 : bit;
signal c11 : bit;
signal c12 : bit;
signal c13 : bit;
signal c14 : bit;
signal c15 : bit;
signal c16 : bit;
signal c17 : bit;
signal c18 : bit;
 
begin
 
c00 <= '0';
 
fa17 : fulladder
   port map (
      addend     => addend_18bit(17),
      augend     => augend_18bit(17),
      carry_in   => c17,
      sum        => adder18_output(17),
      carry      => c18
      );
 
fa16 : fulladder
   port map (
      addend     => addend_18bit(16),
      augend     => augend_18bit(16),
      carry_in   => c16,
      sum        => adder18_output(16),
      carry      => c17
      );
 
fa15 : fulladder
   port map (
      addend     => addend_18bit(15),
      augend     => augend_18bit(15),
      carry_in   => c15,
      sum        => adder18_output(15),
      carry      => c16
      );
 
fa14 : fulladder
   port map (
      addend     => addend_18bit(14),
      augend     => augend_18bit(14),
      carry_in   => c14,
      sum        => adder18_output(14),
      carry      => c15
      );
 
fa13 : fulladder
   port map (
      addend     => addend_18bit(13),
      augend     => augend_18bit(13),
      carry_in   => c13,
      sum        => adder18_output(13),
      carry      => c14
      );
 
fa12 : fulladder
   port map (
      addend     => addend_18bit(12),
      augend     => augend_18bit(12),
      carry_in   => c12,
      sum        => adder18_output(12),
      carry      => c13
      );
 
fa11 : fulladder
   port map (
      addend     => addend_18bit(11),
      augend     => augend_18bit(11),
      carry_in   => c11,
      sum        => adder18_output(11),
      carry      => c12
      );
 
fa10 : fulladder
   port map (
      addend     => addend_18bit(10),
      augend     => augend_18bit(10),
      carry_in   => c10,
      sum        => adder18_output(10),
      carry      => c11
      );
 
fa09 : fulladder
   port map (
      addend     => addend_18bit(09),
      augend     => augend_18bit(09),
      carry_in   => c09,
      sum        => adder18_output(09),
      carry      => c10
      );
 
fa08 : fulladder
   port map (
      addend     => addend_18bit(08),
      augend     => augend_18bit(08),
      carry_in   => c08,
      sum        => adder18_output(08),
      carry      => c09
      );
 
fa07 : fulladder
   port map (
      addend     => addend_18bit(07),
      augend     => augend_18bit(07),
      carry_in   => c07,
      sum        => adder18_output(07),
      carry      => c08
      );
 
fa06 : fulladder
   port map (
      addend     => addend_18bit(06),
      augend     => augend_18bit(06),
      carry_in   => c06,
      sum        => adder18_output(06),
      carry      => c07
      );
 
fa05 : fulladder
   port map (
      addend     => addend_18bit(05),
      augend     => augend_18bit(05),
      carry_in   => c05,
      sum        => adder18_output(05),
      carry      => c06
      );
 
fa04 : fulladder
   port map (
      addend     => addend_18bit(04),
      augend     => augend_18bit(04),
      carry_in   => c04,
      sum        => adder18_output(04),
      carry      => c05
      );
 
fa03 : fulladder
   port map (
      addend     => addend_18bit(03),
      augend     => augend_18bit(03),
      carry_in   => c03,
      sum        => adder18_output(03),
      carry      => c04
      );
 
fa02 : fulladder
   port map (
      addend     => addend_18bit(02),
      augend     => augend_18bit(02),
      carry_in   => c02,
      sum        => adder18_output(02),
      carry      => c03
      );
 
fa01 : fulladder
   port map (
      addend     => addend_18bit(01),
      augend     => augend_18bit(01),
      carry_in   => c01,
      sum        => adder18_output(01),
      carry      => c02
      );
 
fa00 : fulladder
   port map (
      addend     => addend_18bit(00),
      augend     => augend_18bit(00),
      carry_in   => c00,
      sum        => adder18_output(00),
      carry      => c01
      );
 
end structural;

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Subversion Repositories simple_fm_receiver

[/] [simple_fm_receiver/] [trunk/] [source/] [adder_18bit.vhdl] - Blame information for rev 36

Line No.	Rev	Author	Line
1	14	arif_endro	`-- $Id: adder_18bit.vhdl,v 1.3 2005-03-04 08:06:17 arif_endro Exp $`
2	2	arif_endro	`-------------------------------------------------------------------------------`
3			`-- Title : Adder 18 bit`
4			`-- Project : FM Receiver`
5			`-------------------------------------------------------------------------------`
6			`-- File : adder_18bit.vhdl`
7			`-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>`
8			`-- Created : 2004/12/01`
9			`-- Last update :`
10	13	arif_endro	`-- Simulators :`
11	2	arif_endro	`-- Synthesizers:`
12			`-- Target :`
13			`-------------------------------------------------------------------------------`
14			`-- Description : Ripple carry adder 18 bit with output 18 bit`
15			`-------------------------------------------------------------------------------`
16	13	arif_endro	`-- Copyright (C) 2004 Arif E. Nugroho`
17	2	arif_endro	`-- This VHDL design file is an open design; you can redistribute it and/or`
18			`-- modify it and/or implement it after contacting the author`
19			`-------------------------------------------------------------------------------`
20	13	arif_endro	`-------------------------------------------------------------------------------`
21			`--`
22			`-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION`
23			`-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT`
24			`-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE`
25			`-- ASSOCIATED DISCLAIMER.`
26			`--`
27			`-------------------------------------------------------------------------------`
28			`--`
29			-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30			`-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF`
31			`-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO`
32			`-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,`
33			`-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
34			`-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;`
35			`-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,`
36			`-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR`
37			`-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
38			`-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
39			`--`
40			`-------------------------------------------------------------------------------`
41	2	arif_endro
42			`library IEEE;`
43			`use IEEE.STD_LOGIC_1164.ALL;`
44
45			`entity adder_18bit is`
46			`port (`
47			`addend_18bit : in bit_vector (17 downto 0);`
48			`augend_18bit : in bit_vector (17 downto 0);`
49			`adder18_output: out bit_vector (17 downto 0)`
50			`);`
51			`end adder_18bit;`
52
53			`architecture structural of adder_18bit is`
54
55			`component fulladder`
56			`port (`
57			`addend : in bit;`
58			`augend : in bit;`
59			`carry_in : in bit;`
60			`sum : out bit;`
61			`carry : out bit`
62			`);`
63			`end component;`
64
65			`-- internal signal`
66			`signal c00 : bit;`
67			`signal c01 : bit;`
68			`signal c02 : bit;`
69			`signal c03 : bit;`
70			`signal c04 : bit;`
71			`signal c05 : bit;`
72			`signal c06 : bit;`
73			`signal c07 : bit;`
74			`signal c08 : bit;`
75			`signal c09 : bit;`
76			`signal c10 : bit;`
77			`signal c11 : bit;`
78			`signal c12 : bit;`
79			`signal c13 : bit;`
80			`signal c14 : bit;`
81			`signal c15 : bit;`
82			`signal c16 : bit;`
83			`signal c17 : bit;`
84			`signal c18 : bit;`
85
86			`begin`
87
88			`c00 <= '0';`
89
90			`fa17 : fulladder`
91			`port map (`
92			`addend => addend_18bit(17),`
93			`augend => augend_18bit(17),`
94			`carry_in => c17,`
95			`sum => adder18_output(17),`
96			`carry => c18`
97			`);`
98
99			`fa16 : fulladder`
100			`port map (`
101			`addend => addend_18bit(16),`
102			`augend => augend_18bit(16),`
103			`carry_in => c16,`
104			`sum => adder18_output(16),`
105			`carry => c17`
106			`);`
107
108			`fa15 : fulladder`
109			`port map (`
110			`addend => addend_18bit(15),`
111			`augend => augend_18bit(15),`
112			`carry_in => c15,`
113			`sum => adder18_output(15),`
114			`carry => c16`
115			`);`
116
117			`fa14 : fulladder`
118			`port map (`
119			`addend => addend_18bit(14),`
120			`augend => augend_18bit(14),`
121			`carry_in => c14,`
122			`sum => adder18_output(14),`
123			`carry => c15`
124			`);`
125
126			`fa13 : fulladder`
127			`port map (`
128			`addend => addend_18bit(13),`
129			`augend => augend_18bit(13),`
130			`carry_in => c13,`
131			`sum => adder18_output(13),`
132			`carry => c14`
133			`);`
134
135			`fa12 : fulladder`
136			`port map (`
137			`addend => addend_18bit(12),`
138			`augend => augend_18bit(12),`
139			`carry_in => c12,`
140			`sum => adder18_output(12),`
141			`carry => c13`
142			`);`
143
144			`fa11 : fulladder`
145			`port map (`
146			`addend => addend_18bit(11),`
147			`augend => augend_18bit(11),`
148			`carry_in => c11,`
149			`sum => adder18_output(11),`
150			`carry => c12`
151			`);`
152
153			`fa10 : fulladder`
154			`port map (`
155			`addend => addend_18bit(10),`
156			`augend => augend_18bit(10),`
157			`carry_in => c10,`
158			`sum => adder18_output(10),`
159			`carry => c11`
160			`);`
161
162			`fa09 : fulladder`
163			`port map (`
164			`addend => addend_18bit(09),`
165			`augend => augend_18bit(09),`
166			`carry_in => c09,`
167			`sum => adder18_output(09),`
168			`carry => c10`
169			`);`
170
171			`fa08 : fulladder`
172			`port map (`
173			`addend => addend_18bit(08),`
174			`augend => augend_18bit(08),`
175			`carry_in => c08,`
176			`sum => adder18_output(08),`
177			`carry => c09`
178			`);`
179
180			`fa07 : fulladder`
181			`port map (`
182			`addend => addend_18bit(07),`
183			`augend => augend_18bit(07),`
184			`carry_in => c07,`
185			`sum => adder18_output(07),`
186			`carry => c08`
187			`);`
188
189			`fa06 : fulladder`
190			`port map (`
191			`addend => addend_18bit(06),`
192			`augend => augend_18bit(06),`
193			`carry_in => c06,`
194			`sum => adder18_output(06),`
195			`carry => c07`
196			`);`
197
198			`fa05 : fulladder`
199			`port map (`
200			`addend => addend_18bit(05),`
201			`augend => augend_18bit(05),`
202			`carry_in => c05,`
203			`sum => adder18_output(05),`
204			`carry => c06`
205			`);`
206
207			`fa04 : fulladder`
208			`port map (`
209			`addend => addend_18bit(04),`
210			`augend => augend_18bit(04),`
211			`carry_in => c04,`
212			`sum => adder18_output(04),`
213			`carry => c05`
214			`);`
215
216			`fa03 : fulladder`
217			`port map (`
218			`addend => addend_18bit(03),`
219			`augend => augend_18bit(03),`
220			`carry_in => c03,`
221			`sum => adder18_output(03),`
222			`carry => c04`
223			`);`
224
225			`fa02 : fulladder`
226			`port map (`
227			`addend => addend_18bit(02),`
228			`augend => augend_18bit(02),`
229			`carry_in => c02,`
230			`sum => adder18_output(02),`
231			`carry => c03`
232			`);`
233
234			`fa01 : fulladder`
235			`port map (`
236			`addend => addend_18bit(01),`
237			`augend => augend_18bit(01),`
238			`carry_in => c01,`
239			`sum => adder18_output(01),`
240			`carry => c02`
241			`);`
242
243			`fa00 : fulladder`
244			`port map (`
245			`addend => addend_18bit(00),`
246			`augend => augend_18bit(00),`
247			`carry_in => c00,`
248			`sum => adder18_output(00),`
249			`carry => c01`
250			`);`
251
252			`end structural;`