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[/] [simple_fm_receiver/] [trunk/] [source/] [adder_18bit.vhdl] - Blame information for rev 39

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-- $Id: adder_18bit.vhdl,v 1.3 2005-03-04 08:06:17 arif_endro Exp $
-------------------------------------------------------------------------------
-- Title       : Adder 18 bit
-- Project     : FM Receiver 
-------------------------------------------------------------------------------
-- File        : adder_18bit.vhdl
-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
-- Created     : 2004/12/01
-- Last update : 
-- Simulators  : 
-- Synthesizers: 
-- Target      : 
-------------------------------------------------------------------------------
-- Description : Ripple carry adder 18 bit with output 18 bit
-------------------------------------------------------------------------------
-- Copyright (C) 2004 Arif Endro Nugroho
-------------------------------------------------------------------------------
-- 
--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
-- ASSOCIATED DISCLAIMER.
-- 
-------------------------------------------------------------------------------
-- 
--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- 
-------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
 
entity adder_18bit is
   port (
      addend_18bit  : in  bit_vector (17 downto 0);
      augend_18bit  : in  bit_vector (17 downto 0);
      adder18_output: out bit_vector (17 downto 0)
      );
end adder_18bit;
 
architecture structural of adder_18bit is
 
   component fulladder
      port (
      addend        : in   bit;
      augend        : in   bit;
      carry_in      : in   bit;
      sum           : out  bit;
      carry         : out  bit
      );
   end component;
 
-- internal signal
signal c00 : bit;
signal c01 : bit;
signal c02 : bit;
signal c03 : bit;
signal c04 : bit;
signal c05 : bit;
signal c06 : bit;
signal c07 : bit;
signal c08 : bit;
signal c09 : bit;
signal c10 : bit;
signal c11 : bit;
signal c12 : bit;
signal c13 : bit;
signal c14 : bit;
signal c15 : bit;
signal c16 : bit;
signal c17 : bit;
signal c18 : bit;
 
begin
 
c00 <= '0';
 
fa17 : fulladder
   port map (
      addend     => addend_18bit(17),
      augend     => augend_18bit(17),
      carry_in   => c17,
      sum        => adder18_output(17),
      carry      => c18
      );
 
fa16 : fulladder
   port map (
      addend     => addend_18bit(16),
      augend     => augend_18bit(16),
      carry_in   => c16,
      sum        => adder18_output(16),
      carry      => c17
      );
 
fa15 : fulladder
   port map (
      addend     => addend_18bit(15),
      augend     => augend_18bit(15),
      carry_in   => c15,
      sum        => adder18_output(15),
      carry      => c16
      );
 
fa14 : fulladder
   port map (
      addend     => addend_18bit(14),
      augend     => augend_18bit(14),
      carry_in   => c14,
      sum        => adder18_output(14),
      carry      => c15
      );
 
fa13 : fulladder
   port map (
      addend     => addend_18bit(13),
      augend     => augend_18bit(13),
      carry_in   => c13,
      sum        => adder18_output(13),
      carry      => c14
      );
 
fa12 : fulladder
   port map (
      addend     => addend_18bit(12),
      augend     => augend_18bit(12),
      carry_in   => c12,
      sum        => adder18_output(12),
      carry      => c13
      );
 
fa11 : fulladder
   port map (
      addend     => addend_18bit(11),
      augend     => augend_18bit(11),
      carry_in   => c11,
      sum        => adder18_output(11),
      carry      => c12
      );
 
fa10 : fulladder
   port map (
      addend     => addend_18bit(10),
      augend     => augend_18bit(10),
      carry_in   => c10,
      sum        => adder18_output(10),
      carry      => c11
      );
 
fa09 : fulladder
   port map (
      addend     => addend_18bit(09),
      augend     => augend_18bit(09),
      carry_in   => c09,
      sum        => adder18_output(09),
      carry      => c10
      );
 
fa08 : fulladder
   port map (
      addend     => addend_18bit(08),
      augend     => augend_18bit(08),
      carry_in   => c08,
      sum        => adder18_output(08),
      carry      => c09
      );
 
fa07 : fulladder
   port map (
      addend     => addend_18bit(07),
      augend     => augend_18bit(07),
      carry_in   => c07,
      sum        => adder18_output(07),
      carry      => c08
      );
 
fa06 : fulladder
   port map (
      addend     => addend_18bit(06),
      augend     => augend_18bit(06),
      carry_in   => c06,
      sum        => adder18_output(06),
      carry      => c07
      );
 
fa05 : fulladder
   port map (
      addend     => addend_18bit(05),
      augend     => augend_18bit(05),
      carry_in   => c05,
      sum        => adder18_output(05),
      carry      => c06
      );
 
fa04 : fulladder
   port map (
      addend     => addend_18bit(04),
      augend     => augend_18bit(04),
      carry_in   => c04,
      sum        => adder18_output(04),
      carry      => c05
      );
 
fa03 : fulladder
   port map (
      addend     => addend_18bit(03),
      augend     => augend_18bit(03),
      carry_in   => c03,
      sum        => adder18_output(03),
      carry      => c04
      );
 
fa02 : fulladder
   port map (
      addend     => addend_18bit(02),
      augend     => augend_18bit(02),
      carry_in   => c02,
      sum        => adder18_output(02),
      carry      => c03
      );
 
fa01 : fulladder
   port map (
      addend     => addend_18bit(01),
      augend     => augend_18bit(01),
      carry_in   => c01,
      sum        => adder18_output(01),
      carry      => c02
      );
 
fa00 : fulladder
   port map (
      addend     => addend_18bit(00),
      augend     => augend_18bit(00),
      carry_in   => c00,
      sum        => adder18_output(00),
      carry      => c01
      );
 
end structural;

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[/] [simple_fm_receiver/] [trunk/] [source/] [adder_18bit.vhdl] - Blame information for rev 39

Line No.	Rev	Author	Line
1	14	arif_endro	`-- $Id: adder_18bit.vhdl,v 1.3 2005-03-04 08:06:17 arif_endro Exp $`
2	2	arif_endro	`-------------------------------------------------------------------------------`
3			`-- Title : Adder 18 bit`
4			`-- Project : FM Receiver`
5			`-------------------------------------------------------------------------------`
6			`-- File : adder_18bit.vhdl`
7			`-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>`
8			`-- Created : 2004/12/01`
9			`-- Last update :`
10	13	arif_endro	`-- Simulators :`
11	2	arif_endro	`-- Synthesizers:`
12			`-- Target :`
13			`-------------------------------------------------------------------------------`
14			`-- Description : Ripple carry adder 18 bit with output 18 bit`
15			`-------------------------------------------------------------------------------`
16	39	arif_endro	`-- Copyright (C) 2004 Arif Endro Nugroho`
17	2	arif_endro	`-------------------------------------------------------------------------------`
18	13	arif_endro	`--`
19			`-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION`
20			`-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT`
21			`-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE`
22			`-- ASSOCIATED DISCLAIMER.`
23			`--`
24			`-------------------------------------------------------------------------------`
25			`--`
26			-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
27			`-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF`
28			`-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO`
29			`-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,`
30			`-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,`
31			`-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;`
32			`-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,`
33			`-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR`
34			`-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF`
35			`-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
36			`--`
37			`-------------------------------------------------------------------------------`
38	2	arif_endro
39			`library IEEE;`
40			`use IEEE.STD_LOGIC_1164.ALL;`
41
42			`entity adder_18bit is`
43			`port (`
44			`addend_18bit : in bit_vector (17 downto 0);`
45			`augend_18bit : in bit_vector (17 downto 0);`
46			`adder18_output: out bit_vector (17 downto 0)`
47			`);`
48			`end adder_18bit;`
49
50			`architecture structural of adder_18bit is`
51
52			`component fulladder`
53			`port (`
54			`addend : in bit;`
55			`augend : in bit;`
56			`carry_in : in bit;`
57			`sum : out bit;`
58			`carry : out bit`
59			`);`
60			`end component;`
61
62			`-- internal signal`
63			`signal c00 : bit;`
64			`signal c01 : bit;`
65			`signal c02 : bit;`
66			`signal c03 : bit;`
67			`signal c04 : bit;`
68			`signal c05 : bit;`
69			`signal c06 : bit;`
70			`signal c07 : bit;`
71			`signal c08 : bit;`
72			`signal c09 : bit;`
73			`signal c10 : bit;`
74			`signal c11 : bit;`
75			`signal c12 : bit;`
76			`signal c13 : bit;`
77			`signal c14 : bit;`
78			`signal c15 : bit;`
79			`signal c16 : bit;`
80			`signal c17 : bit;`
81			`signal c18 : bit;`
82
83			`begin`
84
85			`c00 <= '0';`
86
87			`fa17 : fulladder`
88			`port map (`
89			`addend => addend_18bit(17),`
90			`augend => augend_18bit(17),`
91			`carry_in => c17,`
92			`sum => adder18_output(17),`
93			`carry => c18`
94			`);`
95
96			`fa16 : fulladder`
97			`port map (`
98			`addend => addend_18bit(16),`
99			`augend => augend_18bit(16),`
100			`carry_in => c16,`
101			`sum => adder18_output(16),`
102			`carry => c17`
103			`);`
104
105			`fa15 : fulladder`
106			`port map (`
107			`addend => addend_18bit(15),`
108			`augend => augend_18bit(15),`
109			`carry_in => c15,`
110			`sum => adder18_output(15),`
111			`carry => c16`
112			`);`
113
114			`fa14 : fulladder`
115			`port map (`
116			`addend => addend_18bit(14),`
117			`augend => augend_18bit(14),`
118			`carry_in => c14,`
119			`sum => adder18_output(14),`
120			`carry => c15`
121			`);`
122
123			`fa13 : fulladder`
124			`port map (`
125			`addend => addend_18bit(13),`
126			`augend => augend_18bit(13),`
127			`carry_in => c13,`
128			`sum => adder18_output(13),`
129			`carry => c14`
130			`);`
131
132			`fa12 : fulladder`
133			`port map (`
134			`addend => addend_18bit(12),`
135			`augend => augend_18bit(12),`
136			`carry_in => c12,`
137			`sum => adder18_output(12),`
138			`carry => c13`
139			`);`
140
141			`fa11 : fulladder`
142			`port map (`
143			`addend => addend_18bit(11),`
144			`augend => augend_18bit(11),`
145			`carry_in => c11,`
146			`sum => adder18_output(11),`
147			`carry => c12`
148			`);`
149
150			`fa10 : fulladder`
151			`port map (`
152			`addend => addend_18bit(10),`
153			`augend => augend_18bit(10),`
154			`carry_in => c10,`
155			`sum => adder18_output(10),`
156			`carry => c11`
157			`);`
158
159			`fa09 : fulladder`
160			`port map (`
161			`addend => addend_18bit(09),`
162			`augend => augend_18bit(09),`
163			`carry_in => c09,`
164			`sum => adder18_output(09),`
165			`carry => c10`
166			`);`
167
168			`fa08 : fulladder`
169			`port map (`
170			`addend => addend_18bit(08),`
171			`augend => augend_18bit(08),`
172			`carry_in => c08,`
173			`sum => adder18_output(08),`
174			`carry => c09`
175			`);`
176
177			`fa07 : fulladder`
178			`port map (`
179			`addend => addend_18bit(07),`
180			`augend => augend_18bit(07),`
181			`carry_in => c07,`
182			`sum => adder18_output(07),`
183			`carry => c08`
184			`);`
185
186			`fa06 : fulladder`
187			`port map (`
188			`addend => addend_18bit(06),`
189			`augend => augend_18bit(06),`
190			`carry_in => c06,`
191			`sum => adder18_output(06),`
192			`carry => c07`
193			`);`
194
195			`fa05 : fulladder`
196			`port map (`
197			`addend => addend_18bit(05),`
198			`augend => augend_18bit(05),`
199			`carry_in => c05,`
200			`sum => adder18_output(05),`
201			`carry => c06`
202			`);`
203
204			`fa04 : fulladder`
205			`port map (`
206			`addend => addend_18bit(04),`
207			`augend => augend_18bit(04),`
208			`carry_in => c04,`
209			`sum => adder18_output(04),`
210			`carry => c05`
211			`);`
212
213			`fa03 : fulladder`
214			`port map (`
215			`addend => addend_18bit(03),`
216			`augend => augend_18bit(03),`
217			`carry_in => c03,`
218			`sum => adder18_output(03),`
219			`carry => c04`
220			`);`
221
222			`fa02 : fulladder`
223			`port map (`
224			`addend => addend_18bit(02),`
225			`augend => augend_18bit(02),`
226			`carry_in => c02,`
227			`sum => adder18_output(02),`
228			`carry => c03`
229			`);`
230
231			`fa01 : fulladder`
232			`port map (`
233			`addend => addend_18bit(01),`
234			`augend => augend_18bit(01),`
235			`carry_in => c01,`
236			`sum => adder18_output(01),`
237			`carry => c02`
238			`);`
239
240			`fa00 : fulladder`
241			`port map (`
242			`addend => addend_18bit(00),`
243			`augend => augend_18bit(00),`
244			`carry_in => c00,`
245			`sum => adder18_output(00),`
246			`carry => c01`
247			`);`
248
249			`end structural;`