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-- ------------------------------------------------------------------------
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arif_endro |
-- Copyright (C) 2004 Arif Endro Nugroho
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arif_endro |
-- All rights reserved.
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arif_endro |
--
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arif_endro |
-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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arif_endro |
--
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arif_endro |
-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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arif_endro |
--
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arif_endro |
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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arif_endro |
--
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-- End Of License.
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-- ------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity fir is
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port(
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clock : in bit;
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clear : in bit;
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fir_in : in bit_vector (11 downto 0); -- <12,4,t>
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dmout : out bit_vector (11 downto 0) -- <12,4,t>
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);
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end fir;
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architecture structural of fir is
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component adder_15bit
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port (
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addend_15bit : in bit_vector (14 downto 0);
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augend_15bit : in bit_vector (14 downto 0);
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adder15_output : out bit_vector (15 downto 0)
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);
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end component;
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component adder_14bit
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port (
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addend_14bit : in bit_vector (13 downto 0);
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augend_14bit : in bit_vector (13 downto 0);
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adder14_output : out bit_vector (14 downto 0)
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);
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end component;
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component adder_13bit
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port (
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addend_13bit : in bit_vector (12 downto 0);
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augend_13bit : in bit_vector (12 downto 0);
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adder13_output : out bit_vector (13 downto 0)
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);
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end component;
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component adder_12bit
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port (
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addend_12bit : in bit_vector (11 downto 0);
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augend_12bit : in bit_vector (11 downto 0);
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adder12_output : out bit_vector (12 downto 0)
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);
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end component;
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signal fir_out : bit_vector (11 downto 0);
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signal fir_in_01 : bit_vector (11 downto 0);
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signal fir_in_02 : bit_vector (11 downto 0);
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signal fir_in_03 : bit_vector (11 downto 0);
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signal fir_in_04 : bit_vector (11 downto 0);
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signal fir_in_05 : bit_vector (11 downto 0);
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signal fir_in_06 : bit_vector (11 downto 0);
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signal fir_in_07 : bit_vector (11 downto 0);
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signal fir_in_08 : bit_vector (11 downto 0);
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signal fir_in_09 : bit_vector (11 downto 0);
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signal fir_in_10 : bit_vector (11 downto 0);
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signal fir_in_11 : bit_vector (11 downto 0);
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signal fir_in_12 : bit_vector (11 downto 0);
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signal fir_in_13 : bit_vector (11 downto 0);
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signal fir_in_14 : bit_vector (11 downto 0);
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signal fir_in_15 : bit_vector (11 downto 0);
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signal fir_in_16 : bit_vector (11 downto 0);
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signal result_adder01 : bit_vector (12 downto 0);
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signal result_adder02 : bit_vector (12 downto 0);
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signal result_adder03 : bit_vector (12 downto 0);
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signal result_adder04 : bit_vector (12 downto 0);
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signal result_adder05 : bit_vector (12 downto 0);
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signal result_adder06 : bit_vector (12 downto 0);
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signal result_adder07 : bit_vector (12 downto 0);
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signal result_adder08 : bit_vector (12 downto 0);
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signal result_adder09 : bit_vector (13 downto 0);
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signal result_adder10 : bit_vector (13 downto 0);
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signal result_adder11 : bit_vector (13 downto 0);
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signal result_adder12 : bit_vector (13 downto 0);
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signal result_adder13 : bit_vector (14 downto 0);
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signal result_adder14 : bit_vector (14 downto 0);
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signal result_adder15 : bit_vector (15 downto 0);
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begin
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fir_in_01 <= fir_in;
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adder01 : adder_12bit
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port map (
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addend_12bit(11 downto 0) => fir_in_01,
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augend_12bit(11 downto 0) => fir_in_02,
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adder12_output => result_adder01
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);
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adder02 : adder_12bit
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port map (
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addend_12bit(11 downto 0) => fir_in_03,
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augend_12bit(11 downto 0) => fir_in_04,
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adder12_output => result_adder02
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);
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adder03 : adder_12bit
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port map (
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addend_12bit(11 downto 0) => fir_in_05,
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augend_12bit(11 downto 0) => fir_in_06,
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adder12_output => result_adder03
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);
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adder04 : adder_12bit
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port map (
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addend_12bit(11 downto 0) => fir_in_07,
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augend_12bit(11 downto 0) => fir_in_08,
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adder12_output => result_adder04
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);
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adder05 : adder_12bit
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port map (
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addend_12bit(11 downto 0) => fir_in_09,
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augend_12bit(11 downto 0) => fir_in_10,
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adder12_output => result_adder05
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);
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adder06 : adder_12bit
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port map (
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addend_12bit(11 downto 0) => fir_in_11,
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augend_12bit(11 downto 0) => fir_in_12,
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adder12_output => result_adder06
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);
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adder07 : adder_12bit
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port map (
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addend_12bit(11 downto 0) => fir_in_13,
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augend_12bit(11 downto 0) => fir_in_14,
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adder12_output => result_adder07
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);
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adder08 : adder_12bit
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port map (
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addend_12bit(11 downto 0) => fir_in_15,
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augend_12bit(11 downto 0) => fir_in_16,
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adder12_output => result_adder08
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);
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adder09 : adder_13bit
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port map (
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addend_13bit(12 downto 0) => result_adder01,
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augend_13bit(12 downto 0) => result_adder02,
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adder13_output => result_adder09
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);
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adder10 : adder_13bit
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port map (
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addend_13bit(12 downto 0) => result_adder03,
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augend_13bit(12 downto 0) => result_adder04,
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adder13_output => result_adder10
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);
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adder11 : adder_13bit
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port map (
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addend_13bit(12 downto 0) => result_adder05,
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augend_13bit(12 downto 0) => result_adder06,
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adder13_output => result_adder11
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);
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adder12 : adder_13bit
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port map (
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addend_13bit(12 downto 0) => result_adder07,
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augend_13bit(12 downto 0) => result_adder08,
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adder13_output => result_adder12
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);
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adder13 : adder_14bit
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port map (
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addend_14bit(13 downto 0) => result_adder09,
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augend_14bit(13 downto 0) => result_adder10,
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adder14_output => result_adder13
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);
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adder14 : adder_14bit
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port map (
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addend_14bit(13 downto 0) => result_adder11,
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augend_14bit(13 downto 0) => result_adder12,
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adder14_output => result_adder14
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);
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adder15 : adder_15bit
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port map (
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addend_15bit(14 downto 0) => result_adder13,
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augend_15bit(14 downto 0) => result_adder14,
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adder15_output => result_adder15
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);
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16 |
arif_endro |
-- FIR constants that have effect on output trasition.
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-- This constant if set to low values (e.g x < 1/8 ) will make
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-- the transition output more looks like steps, noise will be reduced
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-- but it's loss of fidelity of output signal.
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-- for example:
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-- set values to 1/16 will make the output trasition more look's like step
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-- than an curve.
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-- Just try another values to see the result. ^_^
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arif_endro |
fir_out(11) <= (result_adder15(15)); -- 1
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arif_endro |
fir_out(10) <= (result_adder15(14)); -- 1/2
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fir_out(09) <= (result_adder15(13)); -- 1/4
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fir_out(08) <= (result_adder15(12)); -- 1/8
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fir_out(07) <= (result_adder15(11)); -- 1/16
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fir_out(06) <= (result_adder15(10));
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fir_out(05) <= (result_adder15(09));
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fir_out(04) <= (result_adder15(08));
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fir_out(03) <= (result_adder15(07));
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fir_out(02) <= (result_adder15(06));
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fir_out(01) <= (result_adder15(05));
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fir_out(00) <= (result_adder15(04));
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2 |
arif_endro |
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23 |
arif_endro |
-- 20080625
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-- fixme
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-- how to enable clear signal in here... :(
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2 |
arif_endro |
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arif_endro |
-- process (clock, clear)
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process (clock)
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12 |
arif_endro |
begin
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23 |
arif_endro |
-- if (clear = '1') then
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if ((clock = '1') and clock'event) then
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arif_endro |
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arif_endro |
-- dmout <= (others => '0');
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12 |
arif_endro |
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-- elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then
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arif_endro |
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2 |
arif_endro |
fir_in_02 <= fir_in_01;
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fir_in_03 <= fir_in_02;
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fir_in_04 <= fir_in_03;
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fir_in_05 <= fir_in_04;
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fir_in_06 <= fir_in_05;
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fir_in_07 <= fir_in_06;
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fir_in_08 <= fir_in_07;
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fir_in_09 <= fir_in_08;
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fir_in_10 <= fir_in_09;
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fir_in_11 <= fir_in_10;
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fir_in_12 <= fir_in_11;
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fir_in_13 <= fir_in_12;
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fir_in_14 <= fir_in_13;
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fir_in_15 <= fir_in_14;
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fir_in_16 <= fir_in_15;
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dmout <= fir_out;
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end if;
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12 |
arif_endro |
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end process;
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2 |
arif_endro |
end structural;
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