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[/] [simple_fm_receiver/] [trunk/] [source/] [fulladder.vhdl] - Blame information for rev 38

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1 14 arif_endro
-- $Id: fulladder.vhdl,v 1.3 2005-03-04 08:06:19 arif_endro Exp $
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-------------------------------------------------------------------------------
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-- Title       : Full Adder component
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-- Project     : FM Receiver
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-------------------------------------------------------------------------------
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-- File        : fulladder.vhdl
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-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created     : 2004/12/01
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-- Last update : 
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-- Simulators  : 
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-- Synthesizers: 
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-- Target      : 
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-------------------------------------------------------------------------------
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-- Description : Simple one bit adder with carry
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-------------------------------------------------------------------------------
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-- Copyright (C) 2004 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- 
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--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- 
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-------------------------------------------------------------------------------
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-- 
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--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- 
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity fulladder is
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   port (
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     addend   : in   bit;
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     augend   : in   bit;
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     carry_in : in   bit;
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     sum      : out  bit;
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     carry    : out  bit
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     );
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end fulladder;
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architecture data_flow of fulladder is
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begin
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     sum    <= ((addend xor augend) xor carry_in);
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     carry  <= ((addend and augend) or (carry_in and (addend or augend)));
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end data_flow;

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