OpenCores
URL https://opencores.org/ocsvn/simple_fm_receiver/simple_fm_receiver/trunk

Subversion Repositories simple_fm_receiver

[/] [simple_fm_receiver/] [trunk/] [source/] [fulladder.vhdl] - Blame information for rev 46

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 46 arif_endro
-- ------------------------------------------------------------------------
2 39 arif_endro
-- Copyright (C) 2004 Arif Endro Nugroho
3 46 arif_endro
-- All rights reserved.
4 13 arif_endro
-- 
5 46 arif_endro
-- Redistribution and use in source and binary forms, with or without
6
-- modification, are permitted provided that the following conditions
7
-- are met:
8 13 arif_endro
-- 
9 46 arif_endro
-- 1. Redistributions of source code must retain the above copyright
10
--    notice, this list of conditions and the following disclaimer.
11
-- 2. Redistributions in binary form must reproduce the above copyright
12
--    notice, this list of conditions and the following disclaimer in the
13
--    documentation and/or other materials provided with the distribution.
14 13 arif_endro
-- 
15 46 arif_endro
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
16
-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
17
-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18
-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
19
-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21
-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22
-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
24
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25
-- POSSIBILITY OF SUCH DAMAGE.
26 13 arif_endro
-- 
27 46 arif_endro
-- End Of License.
28
-- ------------------------------------------------------------------------
29 2 arif_endro
 
30
library IEEE;
31
use IEEE.STD_LOGIC_1164.ALL;
32
 
33
entity fulladder is
34
   port (
35
     addend   : in   bit;
36
     augend   : in   bit;
37
     carry_in : in   bit;
38
     sum      : out  bit;
39
     carry    : out  bit
40
     );
41
end fulladder;
42
 
43
architecture data_flow of fulladder is
44
begin
45
     sum    <= ((addend xor augend) xor carry_in);
46
     carry  <= ((addend and augend) or (carry_in and (addend or augend)));
47
end data_flow;

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.