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46 |
arif_endro |
-- ------------------------------------------------------------------------
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39 |
arif_endro |
-- Copyright (C) 2004 Arif Endro Nugroho
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46 |
arif_endro |
-- All rights reserved.
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13 |
arif_endro |
--
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46 |
arif_endro |
-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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13 |
arif_endro |
--
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46 |
arif_endro |
-- 1. Redistributions of source code must retain the above copyright
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-- notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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-- notice, this list of conditions and the following disclaimer in the
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-- documentation and/or other materials provided with the distribution.
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13 |
arif_endro |
--
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46 |
arif_endro |
-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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13 |
arif_endro |
--
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46 |
arif_endro |
-- End Of License.
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-- ------------------------------------------------------------------------
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2 |
arif_endro |
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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| 32 |
|
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| 33 |
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entity mult_8bit is
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| 34 |
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port (
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| 35 |
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mult_01 : in bit_vector (07 downto 0);
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| 36 |
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mult_02 : in bit_vector (07 downto 0);
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| 37 |
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result_mult : out bit_vector (15 downto 0)
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| 38 |
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);
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| 39 |
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|
end mult_8bit;
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| 40 |
|
|
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| 41 |
|
|
architecture structural of mult_8bit is
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| 42 |
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component adder_16bit
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| 43 |
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port (
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| 44 |
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addend_16bit : in bit_vector (15 downto 0);
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augend_16bit : in bit_vector (15 downto 0);
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| 46 |
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adder16_output : out bit_vector (16 downto 0)
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);
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end component;
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| 49 |
|
|
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| 50 |
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component adder_16bit_u
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port (
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| 52 |
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addend_16bit : in bit_vector (15 downto 0);
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| 53 |
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augend_16bit : in bit_vector (15 downto 0);
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| 54 |
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adder16_output : out bit_vector (15 downto 0)
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| 55 |
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);
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| 56 |
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end component;
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| 57 |
|
|
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| 58 |
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component adder_15bit
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| 59 |
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port (
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| 60 |
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addend_15bit : in bit_vector (14 downto 0);
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| 61 |
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augend_15bit : in bit_vector (14 downto 0);
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| 62 |
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adder15_output : out bit_vector (15 downto 0)
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| 63 |
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);
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| 64 |
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end component;
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| 65 |
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| 66 |
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component adder_14bit
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port (
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addend_14bit : in bit_vector (13 downto 0);
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augend_14bit : in bit_vector (13 downto 0);
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| 70 |
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adder14_output : out bit_vector (14 downto 0)
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);
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end component;
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component adder_13bit
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port (
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addend_13bit : in bit_vector (12 downto 0);
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augend_13bit : in bit_vector (12 downto 0);
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adder13_output : out bit_vector (13 downto 0)
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| 79 |
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);
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end component;
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component adder_12bit
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port (
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addend_12bit : in bit_vector (11 downto 0);
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augend_12bit : in bit_vector (11 downto 0);
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| 86 |
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adder12_output : out bit_vector (12 downto 0)
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| 87 |
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);
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end component;
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| 89 |
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| 90 |
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component adder_11bit
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port (
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| 92 |
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addend_11bit : in bit_vector (10 downto 0);
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augend_11bit : in bit_vector (10 downto 0);
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| 94 |
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adder11_output : out bit_vector (11 downto 0)
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| 95 |
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);
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end component;
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| 97 |
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| 98 |
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component adder_10bit
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port (
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addend_10bit : in bit_vector (09 downto 0);
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| 101 |
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augend_10bit : in bit_vector (09 downto 0);
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| 102 |
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adder10_output : out bit_vector (10 downto 0)
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| 103 |
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);
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end component;
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| 105 |
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| 106 |
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component adder_09bit
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port (
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| 108 |
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addend_09bit : in bit_vector (08 downto 0);
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| 109 |
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augend_09bit : in bit_vector (08 downto 0);
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| 110 |
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adder09_output : out bit_vector (09 downto 0)
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| 111 |
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);
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end component;
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| 113 |
|
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signal input_phase : bit_vector (07 downto 0);
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signal signal_nco : bit_vector (07 downto 0);
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| 116 |
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| 117 |
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signal sum_part01 : bit_vector (08 downto 0);
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| 118 |
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signal sum_part01_z : bit_vector (08 downto 0);
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| 119 |
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signal sum_part02 : bit_vector (09 downto 0);
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| 120 |
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signal sum_part03 : bit_vector (10 downto 0);
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| 121 |
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signal sum_part04 : bit_vector (11 downto 0);
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| 122 |
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signal sum_part05 : bit_vector (12 downto 0);
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| 123 |
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signal sum_part06 : bit_vector (13 downto 0);
|
| 124 |
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signal sum_part07 : bit_vector (14 downto 0);
|
| 125 |
|
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signal sum_part08_t : bit_vector (15 downto 0);
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| 126 |
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signal sum_part08_o : bit_vector (15 downto 0);
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| 127 |
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signal sum_part08_a : bit_vector (15 downto 0);
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| 128 |
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signal sum_part08 : bit_vector (15 downto 0);
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| 129 |
|
|
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| 130 |
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signal adder_stage_01 : bit_vector (09 downto 0);
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| 131 |
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signal adder_stage_02 : bit_vector (10 downto 0);
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| 132 |
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signal adder_stage_03 : bit_vector (11 downto 0);
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| 133 |
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signal adder_stage_04 : bit_vector (12 downto 0);
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| 134 |
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signal adder_stage_05 : bit_vector (13 downto 0);
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| 135 |
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signal adder_stage_06 : bit_vector (14 downto 0);
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| 136 |
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signal adder_stage_07 : bit_vector (15 downto 0);
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| 137 |
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signal adder_stage_08 : bit_vector (16 downto 0);
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| 138 |
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| 139 |
|
|
begin
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| 140 |
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| 141 |
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sum_part01_z (00) <= '0';
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| 142 |
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sum_part01_z (01) <= '0';
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| 143 |
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sum_part01_z (02) <= '0';
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| 144 |
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sum_part01_z (03) <= '0';
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| 145 |
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sum_part01_z (04) <= '0';
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| 146 |
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sum_part01_z (05) <= '0';
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| 147 |
|
|
sum_part01_z (06) <= '0';
|
| 148 |
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|
sum_part01_z (07) <= '0';
|
| 149 |
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|
sum_part01_z (08) <= '0';
|
| 150 |
|
|
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| 151 |
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|
sum_part01(00) <= signal_nco(0) and input_phase(0);
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| 152 |
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|
sum_part01(01) <= signal_nco(0) and input_phase(1);
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| 153 |
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|
sum_part01(02) <= signal_nco(0) and input_phase(2);
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| 154 |
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|
sum_part01(03) <= signal_nco(0) and input_phase(3);
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| 155 |
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|
sum_part01(04) <= signal_nco(0) and input_phase(4);
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| 156 |
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|
sum_part01(05) <= signal_nco(0) and input_phase(5);
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| 157 |
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|
sum_part01(06) <= signal_nco(0) and input_phase(6);
|
| 158 |
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|
sum_part01(07) <= signal_nco(0) and input_phase(7);
|
| 159 |
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|
sum_part01(08) <= signal_nco(0) and input_phase(7);
|
| 160 |
|
|
|
| 161 |
|
|
sum_part02(00) <= '0';
|
| 162 |
|
|
sum_part02(01) <= signal_nco(1) and input_phase(0);
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| 163 |
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|
sum_part02(02) <= signal_nco(1) and input_phase(1);
|
| 164 |
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|
sum_part02(03) <= signal_nco(1) and input_phase(2);
|
| 165 |
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|
sum_part02(04) <= signal_nco(1) and input_phase(3);
|
| 166 |
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|
sum_part02(05) <= signal_nco(1) and input_phase(4);
|
| 167 |
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|
sum_part02(06) <= signal_nco(1) and input_phase(5);
|
| 168 |
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|
sum_part02(07) <= signal_nco(1) and input_phase(6);
|
| 169 |
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|
sum_part02(08) <= signal_nco(1) and input_phase(7);
|
| 170 |
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|
sum_part02(09) <= signal_nco(1) and input_phase(7);
|
| 171 |
|
|
|
| 172 |
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|
sum_part03(00) <= '0';
|
| 173 |
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|
sum_part03(01) <= '0';
|
| 174 |
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|
sum_part03(02) <= signal_nco(2) and input_phase(0);
|
| 175 |
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|
sum_part03(03) <= signal_nco(2) and input_phase(1);
|
| 176 |
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|
sum_part03(04) <= signal_nco(2) and input_phase(2);
|
| 177 |
|
|
sum_part03(05) <= signal_nco(2) and input_phase(3);
|
| 178 |
|
|
sum_part03(06) <= signal_nco(2) and input_phase(4);
|
| 179 |
|
|
sum_part03(07) <= signal_nco(2) and input_phase(5);
|
| 180 |
|
|
sum_part03(08) <= signal_nco(2) and input_phase(6);
|
| 181 |
|
|
sum_part03(09) <= signal_nco(2) and input_phase(7);
|
| 182 |
|
|
sum_part03(10) <= signal_nco(2) and input_phase(7);
|
| 183 |
|
|
|
| 184 |
|
|
sum_part04(00) <= '0';
|
| 185 |
|
|
sum_part04(01) <= '0';
|
| 186 |
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sum_part04(02) <= '0';
|
| 187 |
|
|
sum_part04(03) <= signal_nco(3) and input_phase(0);
|
| 188 |
|
|
sum_part04(04) <= signal_nco(3) and input_phase(1);
|
| 189 |
|
|
sum_part04(05) <= signal_nco(3) and input_phase(2);
|
| 190 |
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|
sum_part04(06) <= signal_nco(3) and input_phase(3);
|
| 191 |
|
|
sum_part04(07) <= signal_nco(3) and input_phase(4);
|
| 192 |
|
|
sum_part04(08) <= signal_nco(3) and input_phase(5);
|
| 193 |
|
|
sum_part04(09) <= signal_nco(3) and input_phase(6);
|
| 194 |
|
|
sum_part04(10) <= signal_nco(3) and input_phase(7);
|
| 195 |
|
|
sum_part04(11) <= signal_nco(3) and input_phase(7);
|
| 196 |
|
|
|
| 197 |
|
|
sum_part05(00) <= '0';
|
| 198 |
|
|
sum_part05(01) <= '0';
|
| 199 |
|
|
sum_part05(02) <= '0';
|
| 200 |
|
|
sum_part05(03) <= '0';
|
| 201 |
|
|
sum_part05(04) <= signal_nco(4) and input_phase(0);
|
| 202 |
|
|
sum_part05(05) <= signal_nco(4) and input_phase(1);
|
| 203 |
|
|
sum_part05(06) <= signal_nco(4) and input_phase(2);
|
| 204 |
|
|
sum_part05(07) <= signal_nco(4) and input_phase(3);
|
| 205 |
|
|
sum_part05(08) <= signal_nco(4) and input_phase(4);
|
| 206 |
|
|
sum_part05(09) <= signal_nco(4) and input_phase(5);
|
| 207 |
|
|
sum_part05(10) <= signal_nco(4) and input_phase(6);
|
| 208 |
|
|
sum_part05(11) <= signal_nco(4) and input_phase(7);
|
| 209 |
|
|
sum_part05(12) <= signal_nco(4) and input_phase(7);
|
| 210 |
|
|
|
| 211 |
|
|
sum_part06(00) <= '0';
|
| 212 |
|
|
sum_part06(01) <= '0';
|
| 213 |
|
|
sum_part06(02) <= '0';
|
| 214 |
|
|
sum_part06(03) <= '0';
|
| 215 |
|
|
sum_part06(04) <= '0';
|
| 216 |
|
|
sum_part06(05) <= signal_nco(5) and input_phase(0);
|
| 217 |
|
|
sum_part06(06) <= signal_nco(5) and input_phase(1);
|
| 218 |
|
|
sum_part06(07) <= signal_nco(5) and input_phase(2);
|
| 219 |
|
|
sum_part06(08) <= signal_nco(5) and input_phase(3);
|
| 220 |
|
|
sum_part06(09) <= signal_nco(5) and input_phase(4);
|
| 221 |
|
|
sum_part06(10) <= signal_nco(5) and input_phase(5);
|
| 222 |
|
|
sum_part06(11) <= signal_nco(5) and input_phase(6);
|
| 223 |
|
|
sum_part06(12) <= signal_nco(5) and input_phase(7);
|
| 224 |
|
|
sum_part06(13) <= signal_nco(5) and input_phase(7);
|
| 225 |
|
|
|
| 226 |
|
|
sum_part07(00) <= '0';
|
| 227 |
|
|
sum_part07(01) <= '0';
|
| 228 |
|
|
sum_part07(02) <= '0';
|
| 229 |
|
|
sum_part07(03) <= '0';
|
| 230 |
|
|
sum_part07(04) <= '0';
|
| 231 |
|
|
sum_part07(05) <= '0';
|
| 232 |
|
|
sum_part07(06) <= signal_nco(6) and input_phase(0);
|
| 233 |
|
|
sum_part07(07) <= signal_nco(6) and input_phase(1);
|
| 234 |
|
|
sum_part07(08) <= signal_nco(6) and input_phase(2);
|
| 235 |
|
|
sum_part07(09) <= signal_nco(6) and input_phase(3);
|
| 236 |
|
|
sum_part07(10) <= signal_nco(6) and input_phase(4);
|
| 237 |
|
|
sum_part07(11) <= signal_nco(6) and input_phase(5);
|
| 238 |
|
|
sum_part07(12) <= signal_nco(6) and input_phase(6);
|
| 239 |
|
|
sum_part07(13) <= signal_nco(6) and input_phase(7);
|
| 240 |
|
|
sum_part07(14) <= signal_nco(6) and input_phase(7);
|
| 241 |
|
|
|
| 242 |
|
|
sum_part08(00) <= '0';
|
| 243 |
|
|
sum_part08(01) <= '0';
|
| 244 |
|
|
sum_part08(02) <= '0';
|
| 245 |
|
|
sum_part08(03) <= '0';
|
| 246 |
|
|
sum_part08(04) <= '0';
|
| 247 |
|
|
sum_part08(05) <= '0';
|
| 248 |
|
|
sum_part08(06) <= '0';
|
| 249 |
|
|
sum_part08(07) <= signal_nco(7) and input_phase(0);
|
| 250 |
|
|
sum_part08(08) <= signal_nco(7) and input_phase(1);
|
| 251 |
|
|
sum_part08(09) <= signal_nco(7) and input_phase(2);
|
| 252 |
|
|
sum_part08(10) <= signal_nco(7) and input_phase(3);
|
| 253 |
|
|
sum_part08(11) <= signal_nco(7) and input_phase(4);
|
| 254 |
|
|
sum_part08(12) <= signal_nco(7) and input_phase(5);
|
| 255 |
|
|
sum_part08(13) <= signal_nco(7) and input_phase(6);
|
| 256 |
|
|
sum_part08(14) <= signal_nco(7) and input_phase(7);
|
| 257 |
|
|
sum_part08(15) <= signal_nco(7) and input_phase(7);
|
| 258 |
|
|
|
| 259 |
|
|
sum_part08_t (00) <= (not (sum_part08 (00)));
|
| 260 |
|
|
sum_part08_t (01) <= (not (sum_part08 (01)));
|
| 261 |
|
|
sum_part08_t (02) <= (not (sum_part08 (02)));
|
| 262 |
|
|
sum_part08_t (03) <= (not (sum_part08 (03)));
|
| 263 |
|
|
sum_part08_t (04) <= (not (sum_part08 (04)));
|
| 264 |
|
|
sum_part08_t (05) <= (not (sum_part08 (05)));
|
| 265 |
|
|
sum_part08_t (06) <= (not (sum_part08 (06)));
|
| 266 |
|
|
sum_part08_t (07) <= (not (sum_part08 (07)));
|
| 267 |
|
|
sum_part08_t (08) <= (not (sum_part08 (08)));
|
| 268 |
|
|
sum_part08_t (09) <= (not (sum_part08 (09)));
|
| 269 |
|
|
sum_part08_t (10) <= (not (sum_part08 (10)));
|
| 270 |
|
|
sum_part08_t (11) <= (not (sum_part08 (11)));
|
| 271 |
|
|
sum_part08_t (12) <= (not (sum_part08 (12)));
|
| 272 |
|
|
sum_part08_t (13) <= (not (sum_part08 (13)));
|
| 273 |
|
|
sum_part08_t (14) <= (not (sum_part08 (14)));
|
| 274 |
|
|
sum_part08_t (15) <= (not (sum_part08 (15)));
|
| 275 |
|
|
|
| 276 |
|
|
sum_part08_o (00) <= '1';
|
| 277 |
|
|
sum_part08_o (01) <= '0';
|
| 278 |
|
|
sum_part08_o (02) <= '0';
|
| 279 |
|
|
sum_part08_o (03) <= '0';
|
| 280 |
|
|
sum_part08_o (04) <= '0';
|
| 281 |
|
|
sum_part08_o (05) <= '0';
|
| 282 |
|
|
sum_part08_o (06) <= '0';
|
| 283 |
|
|
sum_part08_o (07) <= '0';
|
| 284 |
|
|
sum_part08_o (08) <= '0';
|
| 285 |
|
|
sum_part08_o (09) <= '0';
|
| 286 |
|
|
sum_part08_o (10) <= '0';
|
| 287 |
|
|
sum_part08_o (11) <= '0';
|
| 288 |
|
|
sum_part08_o (12) <= '0';
|
| 289 |
|
|
sum_part08_o (13) <= '0';
|
| 290 |
|
|
sum_part08_o (14) <= '0';
|
| 291 |
|
|
sum_part08_o (15) <= '0';
|
| 292 |
|
|
|
| 293 |
|
|
stage_01 : adder_09bit
|
| 294 |
|
|
port map (
|
| 295 |
|
|
addend_09bit (08 downto 0) => sum_part01_z,
|
| 296 |
|
|
augend_09bit (08 downto 0) => sum_part01,
|
| 297 |
|
|
adder09_output (09 downto 0) => adder_stage_01
|
| 298 |
|
|
);
|
| 299 |
|
|
|
| 300 |
|
|
stage_02 : adder_10bit
|
| 301 |
|
|
port map (
|
| 302 |
|
|
addend_10bit (09 downto 0) => adder_stage_01,
|
| 303 |
|
|
augend_10bit (09 downto 0) => sum_part02,
|
| 304 |
|
|
adder10_output (10 downto 0) => adder_stage_02
|
| 305 |
|
|
);
|
| 306 |
|
|
|
| 307 |
|
|
stage_03 : adder_11bit
|
| 308 |
|
|
port map (
|
| 309 |
|
|
addend_11bit (10 downto 0) => adder_stage_02,
|
| 310 |
|
|
augend_11bit (10 downto 0) => sum_part03,
|
| 311 |
|
|
adder11_output (11 downto 0) => adder_stage_03
|
| 312 |
|
|
);
|
| 313 |
|
|
|
| 314 |
|
|
stage_04 : adder_12bit
|
| 315 |
|
|
port map (
|
| 316 |
|
|
addend_12bit (11 downto 0) => adder_stage_03,
|
| 317 |
|
|
augend_12bit (11 downto 0) => sum_part04,
|
| 318 |
|
|
adder12_output (12 downto 0) => adder_stage_04
|
| 319 |
|
|
);
|
| 320 |
|
|
|
| 321 |
|
|
stage_05 : adder_13bit
|
| 322 |
|
|
port map (
|
| 323 |
|
|
addend_13bit (12 downto 0) => adder_stage_04,
|
| 324 |
|
|
augend_13bit (12 downto 0) => sum_part05,
|
| 325 |
|
|
adder13_output (13 downto 0) => adder_stage_05
|
| 326 |
|
|
);
|
| 327 |
|
|
|
| 328 |
|
|
stage_06 : adder_14bit
|
| 329 |
|
|
port map (
|
| 330 |
|
|
addend_14bit (13 downto 0) => adder_stage_05,
|
| 331 |
|
|
augend_14bit (13 downto 0) => sum_part06,
|
| 332 |
|
|
adder14_output (14 downto 0) => adder_stage_06
|
| 333 |
|
|
);
|
| 334 |
|
|
|
| 335 |
|
|
stage_07 : adder_15bit
|
| 336 |
|
|
port map (
|
| 337 |
|
|
addend_15bit (14 downto 0) => adder_stage_06,
|
| 338 |
|
|
augend_15bit (14 downto 0) => sum_part07,
|
| 339 |
|
|
adder15_output (15 downto 0) => adder_stage_07
|
| 340 |
|
|
);
|
| 341 |
|
|
|
| 342 |
|
|
stage_08_a : adder_16bit_u
|
| 343 |
|
|
port map (
|
| 344 |
|
|
addend_16bit (15 downto 0) => sum_part08_t,
|
| 345 |
|
|
augend_16bit (15 downto 0) => sum_part08_o,
|
| 346 |
|
|
adder16_output (15 downto 0) => sum_part08_a
|
| 347 |
|
|
);
|
| 348 |
|
|
|
| 349 |
|
|
stage_08 : adder_16bit
|
| 350 |
|
|
port map (
|
| 351 |
|
|
addend_16bit (15 downto 0) => adder_stage_07,
|
| 352 |
|
|
augend_16bit (15 downto 0) => sum_part08_a,
|
| 353 |
|
|
adder16_output (16 downto 0) => adder_stage_08
|
| 354 |
|
|
);
|
| 355 |
|
|
|
| 356 |
|
|
input_phase <= mult_01;
|
| 357 |
|
|
signal_nco <= mult_02;
|
| 358 |
|
|
result_mult <= adder_stage_08(15 downto 0);
|
| 359 |
|
|
|
| 360 |
|
|
end structural;
|
