| 1 |
14 |
arif_endro |
-- $Id: mult_8bit.vhdl,v 1.3 2005-03-04 08:06:20 arif_endro Exp $
|
| 2 |
2 |
arif_endro |
-------------------------------------------------------------------------------
|
| 3 |
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|
-- Title : Eight bit multiplier
|
| 4 |
|
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-- Project : FM Receiver
|
| 5 |
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-------------------------------------------------------------------------------
|
| 6 |
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-- File : mult_8bit.vhdl
|
| 7 |
|
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-- Author : "Arif E. Nugroho" <arif_endro@yahoo.com>
|
| 8 |
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-- Created : 2004/12/20
|
| 9 |
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-- Last update :
|
| 10 |
13 |
arif_endro |
-- Simulators :
|
| 11 |
2 |
arif_endro |
-- Synthesizers:
|
| 12 |
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-- Target :
|
| 13 |
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-------------------------------------------------------------------------------
|
| 14 |
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-- Description : Multiplier used in phase detector
|
| 15 |
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-------------------------------------------------------------------------------
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39 |
arif_endro |
-- Copyright (C) 2004 Arif Endro Nugroho
|
| 17 |
13 |
arif_endro |
--------------------------------------------------------------------------------
|
| 18 |
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--
|
| 19 |
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-- THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
|
| 20 |
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
|
| 21 |
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
|
| 22 |
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-- ASSOCIATED DISCLAIMER.
|
| 23 |
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--
|
| 24 |
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--------------------------------------------------------------------------------
|
| 25 |
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--
|
| 26 |
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-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
|
| 27 |
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
|
| 28 |
|
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO
|
| 29 |
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
| 30 |
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
|
| 31 |
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
|
| 32 |
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
|
| 33 |
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
|
| 34 |
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
|
| 35 |
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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| 36 |
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--
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--------------------------------------------------------------------------------
|
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2 |
arif_endro |
|
| 39 |
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library IEEE;
|
| 40 |
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use IEEE.STD_LOGIC_1164.ALL;
|
| 41 |
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|
| 42 |
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entity mult_8bit is
|
| 43 |
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port (
|
| 44 |
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mult_01 : in bit_vector (07 downto 0);
|
| 45 |
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mult_02 : in bit_vector (07 downto 0);
|
| 46 |
|
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result_mult : out bit_vector (15 downto 0)
|
| 47 |
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);
|
| 48 |
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end mult_8bit;
|
| 49 |
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|
| 50 |
|
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architecture structural of mult_8bit is
|
| 51 |
|
|
component adder_16bit
|
| 52 |
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|
port (
|
| 53 |
|
|
addend_16bit : in bit_vector (15 downto 0);
|
| 54 |
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augend_16bit : in bit_vector (15 downto 0);
|
| 55 |
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adder16_output : out bit_vector (16 downto 0)
|
| 56 |
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);
|
| 57 |
|
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end component;
|
| 58 |
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|
| 59 |
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component adder_16bit_u
|
| 60 |
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port (
|
| 61 |
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addend_16bit : in bit_vector (15 downto 0);
|
| 62 |
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augend_16bit : in bit_vector (15 downto 0);
|
| 63 |
|
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adder16_output : out bit_vector (15 downto 0)
|
| 64 |
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);
|
| 65 |
|
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end component;
|
| 66 |
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|
| 67 |
|
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component adder_15bit
|
| 68 |
|
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port (
|
| 69 |
|
|
addend_15bit : in bit_vector (14 downto 0);
|
| 70 |
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augend_15bit : in bit_vector (14 downto 0);
|
| 71 |
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adder15_output : out bit_vector (15 downto 0)
|
| 72 |
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);
|
| 73 |
|
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end component;
|
| 74 |
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|
| 75 |
|
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component adder_14bit
|
| 76 |
|
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port (
|
| 77 |
|
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addend_14bit : in bit_vector (13 downto 0);
|
| 78 |
|
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augend_14bit : in bit_vector (13 downto 0);
|
| 79 |
|
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adder14_output : out bit_vector (14 downto 0)
|
| 80 |
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);
|
| 81 |
|
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end component;
|
| 82 |
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|
| 83 |
|
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component adder_13bit
|
| 84 |
|
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port (
|
| 85 |
|
|
addend_13bit : in bit_vector (12 downto 0);
|
| 86 |
|
|
augend_13bit : in bit_vector (12 downto 0);
|
| 87 |
|
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adder13_output : out bit_vector (13 downto 0)
|
| 88 |
|
|
);
|
| 89 |
|
|
end component;
|
| 90 |
|
|
|
| 91 |
|
|
component adder_12bit
|
| 92 |
|
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port (
|
| 93 |
|
|
addend_12bit : in bit_vector (11 downto 0);
|
| 94 |
|
|
augend_12bit : in bit_vector (11 downto 0);
|
| 95 |
|
|
adder12_output : out bit_vector (12 downto 0)
|
| 96 |
|
|
);
|
| 97 |
|
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end component;
|
| 98 |
|
|
|
| 99 |
|
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component adder_11bit
|
| 100 |
|
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port (
|
| 101 |
|
|
addend_11bit : in bit_vector (10 downto 0);
|
| 102 |
|
|
augend_11bit : in bit_vector (10 downto 0);
|
| 103 |
|
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adder11_output : out bit_vector (11 downto 0)
|
| 104 |
|
|
);
|
| 105 |
|
|
end component;
|
| 106 |
|
|
|
| 107 |
|
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component adder_10bit
|
| 108 |
|
|
port (
|
| 109 |
|
|
addend_10bit : in bit_vector (09 downto 0);
|
| 110 |
|
|
augend_10bit : in bit_vector (09 downto 0);
|
| 111 |
|
|
adder10_output : out bit_vector (10 downto 0)
|
| 112 |
|
|
);
|
| 113 |
|
|
end component;
|
| 114 |
|
|
|
| 115 |
|
|
component adder_09bit
|
| 116 |
|
|
port (
|
| 117 |
|
|
addend_09bit : in bit_vector (08 downto 0);
|
| 118 |
|
|
augend_09bit : in bit_vector (08 downto 0);
|
| 119 |
|
|
adder09_output : out bit_vector (09 downto 0)
|
| 120 |
|
|
);
|
| 121 |
|
|
end component;
|
| 122 |
|
|
|
| 123 |
|
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signal input_phase : bit_vector (07 downto 0);
|
| 124 |
|
|
signal signal_nco : bit_vector (07 downto 0);
|
| 125 |
|
|
|
| 126 |
|
|
signal sum_part01 : bit_vector (08 downto 0);
|
| 127 |
|
|
signal sum_part01_z : bit_vector (08 downto 0);
|
| 128 |
|
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signal sum_part02 : bit_vector (09 downto 0);
|
| 129 |
|
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signal sum_part03 : bit_vector (10 downto 0);
|
| 130 |
|
|
signal sum_part04 : bit_vector (11 downto 0);
|
| 131 |
|
|
signal sum_part05 : bit_vector (12 downto 0);
|
| 132 |
|
|
signal sum_part06 : bit_vector (13 downto 0);
|
| 133 |
|
|
signal sum_part07 : bit_vector (14 downto 0);
|
| 134 |
|
|
signal sum_part08_t : bit_vector (15 downto 0);
|
| 135 |
|
|
signal sum_part08_o : bit_vector (15 downto 0);
|
| 136 |
|
|
signal sum_part08_a : bit_vector (15 downto 0);
|
| 137 |
|
|
signal sum_part08 : bit_vector (15 downto 0);
|
| 138 |
|
|
|
| 139 |
|
|
signal adder_stage_01 : bit_vector (09 downto 0);
|
| 140 |
|
|
signal adder_stage_02 : bit_vector (10 downto 0);
|
| 141 |
|
|
signal adder_stage_03 : bit_vector (11 downto 0);
|
| 142 |
|
|
signal adder_stage_04 : bit_vector (12 downto 0);
|
| 143 |
|
|
signal adder_stage_05 : bit_vector (13 downto 0);
|
| 144 |
|
|
signal adder_stage_06 : bit_vector (14 downto 0);
|
| 145 |
|
|
signal adder_stage_07 : bit_vector (15 downto 0);
|
| 146 |
|
|
signal adder_stage_08 : bit_vector (16 downto 0);
|
| 147 |
|
|
|
| 148 |
|
|
begin
|
| 149 |
|
|
|
| 150 |
|
|
sum_part01_z (00) <= '0';
|
| 151 |
|
|
sum_part01_z (01) <= '0';
|
| 152 |
|
|
sum_part01_z (02) <= '0';
|
| 153 |
|
|
sum_part01_z (03) <= '0';
|
| 154 |
|
|
sum_part01_z (04) <= '0';
|
| 155 |
|
|
sum_part01_z (05) <= '0';
|
| 156 |
|
|
sum_part01_z (06) <= '0';
|
| 157 |
|
|
sum_part01_z (07) <= '0';
|
| 158 |
|
|
sum_part01_z (08) <= '0';
|
| 159 |
|
|
|
| 160 |
|
|
sum_part01(00) <= signal_nco(0) and input_phase(0);
|
| 161 |
|
|
sum_part01(01) <= signal_nco(0) and input_phase(1);
|
| 162 |
|
|
sum_part01(02) <= signal_nco(0) and input_phase(2);
|
| 163 |
|
|
sum_part01(03) <= signal_nco(0) and input_phase(3);
|
| 164 |
|
|
sum_part01(04) <= signal_nco(0) and input_phase(4);
|
| 165 |
|
|
sum_part01(05) <= signal_nco(0) and input_phase(5);
|
| 166 |
|
|
sum_part01(06) <= signal_nco(0) and input_phase(6);
|
| 167 |
|
|
sum_part01(07) <= signal_nco(0) and input_phase(7);
|
| 168 |
|
|
sum_part01(08) <= signal_nco(0) and input_phase(7);
|
| 169 |
|
|
|
| 170 |
|
|
sum_part02(00) <= '0';
|
| 171 |
|
|
sum_part02(01) <= signal_nco(1) and input_phase(0);
|
| 172 |
|
|
sum_part02(02) <= signal_nco(1) and input_phase(1);
|
| 173 |
|
|
sum_part02(03) <= signal_nco(1) and input_phase(2);
|
| 174 |
|
|
sum_part02(04) <= signal_nco(1) and input_phase(3);
|
| 175 |
|
|
sum_part02(05) <= signal_nco(1) and input_phase(4);
|
| 176 |
|
|
sum_part02(06) <= signal_nco(1) and input_phase(5);
|
| 177 |
|
|
sum_part02(07) <= signal_nco(1) and input_phase(6);
|
| 178 |
|
|
sum_part02(08) <= signal_nco(1) and input_phase(7);
|
| 179 |
|
|
sum_part02(09) <= signal_nco(1) and input_phase(7);
|
| 180 |
|
|
|
| 181 |
|
|
sum_part03(00) <= '0';
|
| 182 |
|
|
sum_part03(01) <= '0';
|
| 183 |
|
|
sum_part03(02) <= signal_nco(2) and input_phase(0);
|
| 184 |
|
|
sum_part03(03) <= signal_nco(2) and input_phase(1);
|
| 185 |
|
|
sum_part03(04) <= signal_nco(2) and input_phase(2);
|
| 186 |
|
|
sum_part03(05) <= signal_nco(2) and input_phase(3);
|
| 187 |
|
|
sum_part03(06) <= signal_nco(2) and input_phase(4);
|
| 188 |
|
|
sum_part03(07) <= signal_nco(2) and input_phase(5);
|
| 189 |
|
|
sum_part03(08) <= signal_nco(2) and input_phase(6);
|
| 190 |
|
|
sum_part03(09) <= signal_nco(2) and input_phase(7);
|
| 191 |
|
|
sum_part03(10) <= signal_nco(2) and input_phase(7);
|
| 192 |
|
|
|
| 193 |
|
|
sum_part04(00) <= '0';
|
| 194 |
|
|
sum_part04(01) <= '0';
|
| 195 |
|
|
sum_part04(02) <= '0';
|
| 196 |
|
|
sum_part04(03) <= signal_nco(3) and input_phase(0);
|
| 197 |
|
|
sum_part04(04) <= signal_nco(3) and input_phase(1);
|
| 198 |
|
|
sum_part04(05) <= signal_nco(3) and input_phase(2);
|
| 199 |
|
|
sum_part04(06) <= signal_nco(3) and input_phase(3);
|
| 200 |
|
|
sum_part04(07) <= signal_nco(3) and input_phase(4);
|
| 201 |
|
|
sum_part04(08) <= signal_nco(3) and input_phase(5);
|
| 202 |
|
|
sum_part04(09) <= signal_nco(3) and input_phase(6);
|
| 203 |
|
|
sum_part04(10) <= signal_nco(3) and input_phase(7);
|
| 204 |
|
|
sum_part04(11) <= signal_nco(3) and input_phase(7);
|
| 205 |
|
|
|
| 206 |
|
|
sum_part05(00) <= '0';
|
| 207 |
|
|
sum_part05(01) <= '0';
|
| 208 |
|
|
sum_part05(02) <= '0';
|
| 209 |
|
|
sum_part05(03) <= '0';
|
| 210 |
|
|
sum_part05(04) <= signal_nco(4) and input_phase(0);
|
| 211 |
|
|
sum_part05(05) <= signal_nco(4) and input_phase(1);
|
| 212 |
|
|
sum_part05(06) <= signal_nco(4) and input_phase(2);
|
| 213 |
|
|
sum_part05(07) <= signal_nco(4) and input_phase(3);
|
| 214 |
|
|
sum_part05(08) <= signal_nco(4) and input_phase(4);
|
| 215 |
|
|
sum_part05(09) <= signal_nco(4) and input_phase(5);
|
| 216 |
|
|
sum_part05(10) <= signal_nco(4) and input_phase(6);
|
| 217 |
|
|
sum_part05(11) <= signal_nco(4) and input_phase(7);
|
| 218 |
|
|
sum_part05(12) <= signal_nco(4) and input_phase(7);
|
| 219 |
|
|
|
| 220 |
|
|
sum_part06(00) <= '0';
|
| 221 |
|
|
sum_part06(01) <= '0';
|
| 222 |
|
|
sum_part06(02) <= '0';
|
| 223 |
|
|
sum_part06(03) <= '0';
|
| 224 |
|
|
sum_part06(04) <= '0';
|
| 225 |
|
|
sum_part06(05) <= signal_nco(5) and input_phase(0);
|
| 226 |
|
|
sum_part06(06) <= signal_nco(5) and input_phase(1);
|
| 227 |
|
|
sum_part06(07) <= signal_nco(5) and input_phase(2);
|
| 228 |
|
|
sum_part06(08) <= signal_nco(5) and input_phase(3);
|
| 229 |
|
|
sum_part06(09) <= signal_nco(5) and input_phase(4);
|
| 230 |
|
|
sum_part06(10) <= signal_nco(5) and input_phase(5);
|
| 231 |
|
|
sum_part06(11) <= signal_nco(5) and input_phase(6);
|
| 232 |
|
|
sum_part06(12) <= signal_nco(5) and input_phase(7);
|
| 233 |
|
|
sum_part06(13) <= signal_nco(5) and input_phase(7);
|
| 234 |
|
|
|
| 235 |
|
|
sum_part07(00) <= '0';
|
| 236 |
|
|
sum_part07(01) <= '0';
|
| 237 |
|
|
sum_part07(02) <= '0';
|
| 238 |
|
|
sum_part07(03) <= '0';
|
| 239 |
|
|
sum_part07(04) <= '0';
|
| 240 |
|
|
sum_part07(05) <= '0';
|
| 241 |
|
|
sum_part07(06) <= signal_nco(6) and input_phase(0);
|
| 242 |
|
|
sum_part07(07) <= signal_nco(6) and input_phase(1);
|
| 243 |
|
|
sum_part07(08) <= signal_nco(6) and input_phase(2);
|
| 244 |
|
|
sum_part07(09) <= signal_nco(6) and input_phase(3);
|
| 245 |
|
|
sum_part07(10) <= signal_nco(6) and input_phase(4);
|
| 246 |
|
|
sum_part07(11) <= signal_nco(6) and input_phase(5);
|
| 247 |
|
|
sum_part07(12) <= signal_nco(6) and input_phase(6);
|
| 248 |
|
|
sum_part07(13) <= signal_nco(6) and input_phase(7);
|
| 249 |
|
|
sum_part07(14) <= signal_nco(6) and input_phase(7);
|
| 250 |
|
|
|
| 251 |
|
|
sum_part08(00) <= '0';
|
| 252 |
|
|
sum_part08(01) <= '0';
|
| 253 |
|
|
sum_part08(02) <= '0';
|
| 254 |
|
|
sum_part08(03) <= '0';
|
| 255 |
|
|
sum_part08(04) <= '0';
|
| 256 |
|
|
sum_part08(05) <= '0';
|
| 257 |
|
|
sum_part08(06) <= '0';
|
| 258 |
|
|
sum_part08(07) <= signal_nco(7) and input_phase(0);
|
| 259 |
|
|
sum_part08(08) <= signal_nco(7) and input_phase(1);
|
| 260 |
|
|
sum_part08(09) <= signal_nco(7) and input_phase(2);
|
| 261 |
|
|
sum_part08(10) <= signal_nco(7) and input_phase(3);
|
| 262 |
|
|
sum_part08(11) <= signal_nco(7) and input_phase(4);
|
| 263 |
|
|
sum_part08(12) <= signal_nco(7) and input_phase(5);
|
| 264 |
|
|
sum_part08(13) <= signal_nco(7) and input_phase(6);
|
| 265 |
|
|
sum_part08(14) <= signal_nco(7) and input_phase(7);
|
| 266 |
|
|
sum_part08(15) <= signal_nco(7) and input_phase(7);
|
| 267 |
|
|
|
| 268 |
|
|
sum_part08_t (00) <= (not (sum_part08 (00)));
|
| 269 |
|
|
sum_part08_t (01) <= (not (sum_part08 (01)));
|
| 270 |
|
|
sum_part08_t (02) <= (not (sum_part08 (02)));
|
| 271 |
|
|
sum_part08_t (03) <= (not (sum_part08 (03)));
|
| 272 |
|
|
sum_part08_t (04) <= (not (sum_part08 (04)));
|
| 273 |
|
|
sum_part08_t (05) <= (not (sum_part08 (05)));
|
| 274 |
|
|
sum_part08_t (06) <= (not (sum_part08 (06)));
|
| 275 |
|
|
sum_part08_t (07) <= (not (sum_part08 (07)));
|
| 276 |
|
|
sum_part08_t (08) <= (not (sum_part08 (08)));
|
| 277 |
|
|
sum_part08_t (09) <= (not (sum_part08 (09)));
|
| 278 |
|
|
sum_part08_t (10) <= (not (sum_part08 (10)));
|
| 279 |
|
|
sum_part08_t (11) <= (not (sum_part08 (11)));
|
| 280 |
|
|
sum_part08_t (12) <= (not (sum_part08 (12)));
|
| 281 |
|
|
sum_part08_t (13) <= (not (sum_part08 (13)));
|
| 282 |
|
|
sum_part08_t (14) <= (not (sum_part08 (14)));
|
| 283 |
|
|
sum_part08_t (15) <= (not (sum_part08 (15)));
|
| 284 |
|
|
|
| 285 |
|
|
sum_part08_o (00) <= '1';
|
| 286 |
|
|
sum_part08_o (01) <= '0';
|
| 287 |
|
|
sum_part08_o (02) <= '0';
|
| 288 |
|
|
sum_part08_o (03) <= '0';
|
| 289 |
|
|
sum_part08_o (04) <= '0';
|
| 290 |
|
|
sum_part08_o (05) <= '0';
|
| 291 |
|
|
sum_part08_o (06) <= '0';
|
| 292 |
|
|
sum_part08_o (07) <= '0';
|
| 293 |
|
|
sum_part08_o (08) <= '0';
|
| 294 |
|
|
sum_part08_o (09) <= '0';
|
| 295 |
|
|
sum_part08_o (10) <= '0';
|
| 296 |
|
|
sum_part08_o (11) <= '0';
|
| 297 |
|
|
sum_part08_o (12) <= '0';
|
| 298 |
|
|
sum_part08_o (13) <= '0';
|
| 299 |
|
|
sum_part08_o (14) <= '0';
|
| 300 |
|
|
sum_part08_o (15) <= '0';
|
| 301 |
|
|
|
| 302 |
|
|
stage_01 : adder_09bit
|
| 303 |
|
|
port map (
|
| 304 |
|
|
addend_09bit (08 downto 0) => sum_part01_z,
|
| 305 |
|
|
augend_09bit (08 downto 0) => sum_part01,
|
| 306 |
|
|
adder09_output (09 downto 0) => adder_stage_01
|
| 307 |
|
|
);
|
| 308 |
|
|
|
| 309 |
|
|
stage_02 : adder_10bit
|
| 310 |
|
|
port map (
|
| 311 |
|
|
addend_10bit (09 downto 0) => adder_stage_01,
|
| 312 |
|
|
augend_10bit (09 downto 0) => sum_part02,
|
| 313 |
|
|
adder10_output (10 downto 0) => adder_stage_02
|
| 314 |
|
|
);
|
| 315 |
|
|
|
| 316 |
|
|
stage_03 : adder_11bit
|
| 317 |
|
|
port map (
|
| 318 |
|
|
addend_11bit (10 downto 0) => adder_stage_02,
|
| 319 |
|
|
augend_11bit (10 downto 0) => sum_part03,
|
| 320 |
|
|
adder11_output (11 downto 0) => adder_stage_03
|
| 321 |
|
|
);
|
| 322 |
|
|
|
| 323 |
|
|
stage_04 : adder_12bit
|
| 324 |
|
|
port map (
|
| 325 |
|
|
addend_12bit (11 downto 0) => adder_stage_03,
|
| 326 |
|
|
augend_12bit (11 downto 0) => sum_part04,
|
| 327 |
|
|
adder12_output (12 downto 0) => adder_stage_04
|
| 328 |
|
|
);
|
| 329 |
|
|
|
| 330 |
|
|
stage_05 : adder_13bit
|
| 331 |
|
|
port map (
|
| 332 |
|
|
addend_13bit (12 downto 0) => adder_stage_04,
|
| 333 |
|
|
augend_13bit (12 downto 0) => sum_part05,
|
| 334 |
|
|
adder13_output (13 downto 0) => adder_stage_05
|
| 335 |
|
|
);
|
| 336 |
|
|
|
| 337 |
|
|
stage_06 : adder_14bit
|
| 338 |
|
|
port map (
|
| 339 |
|
|
addend_14bit (13 downto 0) => adder_stage_05,
|
| 340 |
|
|
augend_14bit (13 downto 0) => sum_part06,
|
| 341 |
|
|
adder14_output (14 downto 0) => adder_stage_06
|
| 342 |
|
|
);
|
| 343 |
|
|
|
| 344 |
|
|
stage_07 : adder_15bit
|
| 345 |
|
|
port map (
|
| 346 |
|
|
addend_15bit (14 downto 0) => adder_stage_06,
|
| 347 |
|
|
augend_15bit (14 downto 0) => sum_part07,
|
| 348 |
|
|
adder15_output (15 downto 0) => adder_stage_07
|
| 349 |
|
|
);
|
| 350 |
|
|
|
| 351 |
|
|
stage_08_a : adder_16bit_u
|
| 352 |
|
|
port map (
|
| 353 |
|
|
addend_16bit (15 downto 0) => sum_part08_t,
|
| 354 |
|
|
augend_16bit (15 downto 0) => sum_part08_o,
|
| 355 |
|
|
adder16_output (15 downto 0) => sum_part08_a
|
| 356 |
|
|
);
|
| 357 |
|
|
|
| 358 |
|
|
stage_08 : adder_16bit
|
| 359 |
|
|
port map (
|
| 360 |
|
|
addend_16bit (15 downto 0) => adder_stage_07,
|
| 361 |
|
|
augend_16bit (15 downto 0) => sum_part08_a,
|
| 362 |
|
|
adder16_output (16 downto 0) => adder_stage_08
|
| 363 |
|
|
);
|
| 364 |
|
|
|
| 365 |
|
|
input_phase <= mult_01;
|
| 366 |
|
|
signal_nco <= mult_02;
|
| 367 |
|
|
result_mult <= adder_stage_08(15 downto 0);
|
| 368 |
|
|
|
| 369 |
|
|
end structural;
|
