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1 23 arif_endro
-- $Id: nco.vhdl,v 1.4 2008-06-26 06:16:04 arif_endro Exp $
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-------------------------------------------------------------------------------
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-- Title       : NCO (Numerical Controlled Oscillator)
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-- Project     : FM Receiver 
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-------------------------------------------------------------------------------
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-- File        : nco.vhdl
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-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created     : 2004/10/27
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-- Last update : 
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-- Simulators  : 
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-- Synthesizers: 
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-- Target      : 
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-------------------------------------------------------------------------------
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-- Description : Works like VCO in analog PLL
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-------------------------------------------------------------------------------
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-- Copyright (C) 2004 Arif E. Nugroho
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-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- 
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--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- 
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-------------------------------------------------------------------------------
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-- 
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--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- 
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-------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.all;
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entity nco is
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      port (
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           clock       : in  bit;
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           clear       : in  bit;
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           input_nco   : in  bit_vector (17 downto 0);
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           offset      : in  bit_vector (17 downto 0);
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           output_nco  : out bit_vector (07 downto 0)
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           );
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end nco;
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architecture structural of nco is
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   component addacc
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     port (
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           clock       : in  bit;
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           acc         : in  bit_vector (17 downto 0);
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           result      : out bit_vector (17 downto 0);
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           offset      : in  bit_vector (17 downto 0)
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           );
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   end component;
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   component rom
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     port (
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           address     : in  bit_vector (09 downto 0);
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           data        : out bit_vector (07 downto 0)
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           );
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   end component;
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   signal adder_output : bit_vector (17 downto 0);
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   signal address_in   : bit_vector (09 downto 0);
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   signal output_rom   : bit_vector (07 downto 0);
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begin
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 myaddacc  : addacc
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     port map (
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              clock                 => clock,
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              acc                   => input_nco,
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              result (17 downto 0)  => adder_output,
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              offset                => offset
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              );
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 myrom     : rom
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     port map (
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              address (09 downto 0) => address_in,
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              data    (07 downto 0) => output_rom
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              );
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   address_in (09) <= (adder_output(17));
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   address_in (08) <= (adder_output(16));
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   address_in (07) <= (adder_output(15));
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   address_in (06) <= (adder_output(14));
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   address_in (05) <= (adder_output(13));
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   address_in (04) <= (adder_output(12));
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   address_in (03) <= (adder_output(11));
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   address_in (02) <= (adder_output(10));
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   address_in (01) <= (adder_output(09));
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   address_in (00) <= (adder_output(08));
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--   process (clock, clear)
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   process (clock)
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   begin
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-- 20080625
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-- fixme
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-- how to enable clear signal in here... :(
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--   if    (clear = '1') then
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   if ((clock = '1') and clock'event) then
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--      output_nco      <= (others => '0');
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--   elsif (((clock = '1') and (not(clear) = '1')) and clock'event) then
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        output_nco (07) <= (output_rom(07));
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        output_nco (06) <= (output_rom(06));
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        output_nco (05) <= (output_rom(05));
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        output_nco (04) <= (output_rom(04));
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        output_nco (03) <= (output_rom(03));
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        output_nco (02) <= (output_rom(02));
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        output_nco (01) <= (output_rom(01));
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        output_nco (00) <= (output_rom(00));
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   end if;
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   end process;
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end structural;

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