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[/] [simple_fm_receiver/] [trunk/] [source/] [phase_detector.vhdl] - Blame information for rev 46

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1 46 arif_endro
-- ------------------------------------------------------------------------
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-- Copyright (C) 2004 Arif Endro Nugroho
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-- All rights reserved.
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-- 
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-- Redistribution and use in source and binary forms, with or without
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-- modification, are permitted provided that the following conditions
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-- are met:
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-- 
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-- 1. Redistributions of source code must retain the above copyright
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--    notice, this list of conditions and the following disclaimer.
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-- 2. Redistributions in binary form must reproduce the above copyright
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--    notice, this list of conditions and the following disclaimer in the
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--    documentation and/or other materials provided with the distribution.
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-- 
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-- THIS SOFTWARE IS PROVIDED BY ARIF ENDRO NUGROHO "AS IS" AND ANY EXPRESS
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-- OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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-- WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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-- DISCLAIMED. IN NO EVENT SHALL ARIF ENDRO NUGROHO BE LIABLE FOR ANY
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-- DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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-- POSSIBILITY OF SUCH DAMAGE.
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-- 
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-- End Of License.
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-- ------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity phase_detector is
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   port (
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   clock        : in  bit;
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   signal_input : in  bit_vector (07 downto 0);
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   signal_nco   : in  bit_vector (07 downto 0);
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   phase_output : out bit_vector (07 downto 0)
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   );
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end phase_detector;
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architecture structural of phase_detector is
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   component mult_8bit
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   port (
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   mult_01    : in  bit_vector (07 downto 00);
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   mult_02    : in  bit_vector (07 downto 00);
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   result_mult: out bit_vector (15 downto 00)
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   );
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   end component;
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   signal output_mult  : bit_vector (15 downto 0);
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   begin
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phase_mult: mult_8bit
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   port map (
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   mult_01     (07 downto 0)  => signal_input,
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   mult_02     (07 downto 0)  => signal_nco,
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   result_mult (15 downto 0)  => output_mult
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   );
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   process (clock)
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   begin
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   if ((clock = '1') and clock'event) then
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        phase_output <= output_mult(15 downto 8);
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   end if;
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   end process;
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end structural;

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