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[/] [simple_fm_receiver/] [trunk/] [source/] [sub_12bit.vhdl] - Blame information for rev 36

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1 14 arif_endro
-- $Id: sub_12bit.vhdl,v 1.3 2005-03-04 08:06:21 arif_endro Exp $
2 2 arif_endro
-------------------------------------------------------------------------------
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-- Title       : Subtractor 12 bit
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-- Project     : FM Receiver 
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-------------------------------------------------------------------------------
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-- File        : sub_12bit.vhdl
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-- Author      : "Arif E. Nugroho" <arif_endro@yahoo.com>
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-- Created     : 2004/12/01
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-- Last update : 
10 13 arif_endro
-- Simulators  : 
11 2 arif_endro
-- Synthesizers: 
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-- Target      : 
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-------------------------------------------------------------------------------
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-- Description : Subtractor 12 bit used in loop filter
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-------------------------------------------------------------------------------
16 13 arif_endro
-- Copyright (C) 2004 Arif E. Nugroho
17 2 arif_endro
-- This VHDL design file is an open design; you can redistribute it and/or
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-- modify it and/or implement it after contacting the author
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-------------------------------------------------------------------------------
20 13 arif_endro
-------------------------------------------------------------------------------
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-- 
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--      THIS SOURCE FILE MAY BE USED AND DISTRIBUTED WITHOUT RESTRICTION
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-- PROVIDED THAT THIS COPYRIGHT STATEMENT IS NOT REMOVED FROM THE FILE AND THAT
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-- ANY DERIVATIVE WORK CONTAINS THE ORIGINAL COPYRIGHT NOTICE AND THE
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-- ASSOCIATED DISCLAIMER.
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-- 
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-------------------------------------------------------------------------------
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-- 
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--      THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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-- IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
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-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
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-- EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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-- SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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-- PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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-- OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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-- WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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-- OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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-- 
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-------------------------------------------------------------------------------
41 2 arif_endro
 
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity sub_12bit is
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   port (
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      addend_12bit           : in  bit_vector (11 downto 0);
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      subtrahend_12bit       : in  bit_vector (11 downto 0);
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      subtractor12_output    : out bit_vector (11 downto 0)
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      );
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end sub_12bit;
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architecture structural of sub_12bit is
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   component fulladder
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      port (
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      addend        : in   bit;
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      augend        : in   bit;
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      carry_in      : in   bit;
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      sum           : out  bit;
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      carry         : out  bit
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      );
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   end component;
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-- internal signal
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signal c00 : bit;
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signal c01 : bit;
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signal c02 : bit;
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signal c03 : bit;
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signal c04 : bit;
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signal c05 : bit;
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signal c06 : bit;
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signal c07 : bit;
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signal c08 : bit;
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signal c09 : bit;
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signal c10 : bit;
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signal c11 : bit;
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signal c12 : bit;
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signal augend_12bit    : bit_vector (11 downto 0);
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signal adder12_output  : bit_vector (11 downto 0);
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begin
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c00               <= '1'; -- add one to get 2's complement
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-- first complement
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augend_12bit (11) <= not (subtrahend_12bit (11));
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augend_12bit (10) <= not (subtrahend_12bit (10));
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augend_12bit (09) <= not (subtrahend_12bit (09));
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augend_12bit (08) <= not (subtrahend_12bit (08));
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augend_12bit (07) <= not (subtrahend_12bit (07));
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augend_12bit (06) <= not (subtrahend_12bit (06));
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augend_12bit (05) <= not (subtrahend_12bit (05));
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augend_12bit (04) <= not (subtrahend_12bit (04));
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augend_12bit (03) <= not (subtrahend_12bit (03));
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augend_12bit (02) <= not (subtrahend_12bit (02));
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augend_12bit (01) <= not (subtrahend_12bit (01));
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augend_12bit (00) <= not (subtrahend_12bit (00));
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subtractor12_output <= adder12_output;
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fa11 : fulladder
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   port map (
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      addend     => addend_12bit(11),
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      augend     => augend_12bit(11),
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      carry_in   => c11,
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      sum        => adder12_output(11),
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      carry      => c12
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      );
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fa10 : fulladder
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   port map (
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      addend     => addend_12bit(10),
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      augend     => augend_12bit(10),
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      carry_in   => c10,
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      sum        => adder12_output(10),
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      carry      => c11
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      );
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fa09 : fulladder
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   port map (
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      addend     => addend_12bit(09),
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      augend     => augend_12bit(09),
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      carry_in   => c09,
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      sum        => adder12_output(09),
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      carry      => c10
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      );
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fa08 : fulladder
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   port map (
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      addend     => addend_12bit(08),
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      augend     => augend_12bit(08),
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      carry_in   => c08,
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      sum        => adder12_output(08),
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      carry      => c09
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      );
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fa07 : fulladder
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   port map (
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      addend     => addend_12bit(07),
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      augend     => augend_12bit(07),
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      carry_in   => c07,
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      sum        => adder12_output(07),
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      carry      => c08
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      );
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fa06 : fulladder
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   port map (
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      addend     => addend_12bit(06),
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      augend     => augend_12bit(06),
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      carry_in   => c06,
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      sum        => adder12_output(06),
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      carry      => c07
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      );
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fa05 : fulladder
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   port map (
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      addend     => addend_12bit(05),
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      augend     => augend_12bit(05),
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      carry_in   => c05,
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      sum        => adder12_output(05),
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      carry      => c06
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      );
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fa04 : fulladder
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   port map (
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      addend     => addend_12bit(04),
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      augend     => augend_12bit(04),
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      carry_in   => c04,
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      sum        => adder12_output(04),
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      carry      => c05
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      );
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fa03 : fulladder
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   port map (
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      addend     => addend_12bit(03),
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      augend     => augend_12bit(03),
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      carry_in   => c03,
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      sum        => adder12_output(03),
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      carry      => c04
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      );
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fa02 : fulladder
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   port map (
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      addend     => addend_12bit(02),
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      augend     => augend_12bit(02),
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      carry_in   => c02,
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      sum        => adder12_output(02),
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      carry      => c03
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      );
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fa01 : fulladder
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   port map (
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      addend     => addend_12bit(01),
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      augend     => augend_12bit(01),
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      carry_in   => c01,
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      sum        => adder12_output(01),
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      carry      => c02
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      );
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fa00 : fulladder
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   port map (
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      addend     => addend_12bit(00),
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      augend     => augend_12bit(00),
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      carry_in   => c00,
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      sum        => adder12_output(00),
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      carry      => c01
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      );
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end structural;

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