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/////////////////////////////////////////////////////////////////////
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//// ////
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//// OpenCores Simple Programmable Interrupt Controller ////
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//// ////
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//// Author: Richard Herveille ////
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//// richard@asics.ws ////
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//// www.asics.ws ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2002 Richard Herveille ////
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//// richard@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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rherveille |
// $Id: simple_pic.v,v 1.3 2002-12-24 10:26:51 rherveille Exp $
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//
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// $Date: 2002-12-24 10:26:51 $
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// $Revision: 1.3 $
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// $Author: rherveille $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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rherveille |
// Revision 1.2 2002/12/22 16:11:03 rherveille
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// *** empty log message ***
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//
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//
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//
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// This is a simple Programmable Interrupt Controller.
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// The number of interrupts is depending on the databus size.
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// There's one interrupt input per databit (i.e. 16 interrupts for a 16
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// bit databus).
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// All attached devices share the same CPU priority level.
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//
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//
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//
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// Registers:
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//
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// 0x00: EdgeEnable Register
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// bits 7:0 R/W Edge Enable '1' = edge triggered interrupt source
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// '0' = level triggered interrupt source
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// 0x01: PolarityRegister
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// bits 7:0 R/W Polarity '1' = high level / rising edge
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// '0' = low level / falling edge
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// 0x02: MaskRegister
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// bits 7:0 R/W Mask '1' = interrupt masked (disabled)
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// '0' = interrupt not masked (enabled)
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// 0x03: PendingRegister
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// bits 7:0 R/W Pending '1' = interrupt pending
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// '0' = no interrupt pending
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//
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// A CPU interrupt is generated when an interrupt is pending and its
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// MASK bit is cleared.
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//
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//
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//
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// HOWTO:
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//
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// Clearing pending interrupts:
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// Writing a '1' to a bit in the interrupt pending register clears the
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// interrupt. Make sure to clear the interrupt at the source before
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// writing to the interrupt pending register. Otherwise the interrupt
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// will be set again.
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//
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// Priority based interrupts:
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// Upon reception of an interrupt, check the interrupt register and
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// determine the highest priority interrupt. Mask all interrupts from the
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// current level to the lowest level. This negates the interrupt line, and
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// makes sure only interrupts with a higher level are triggered. After
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// completion of the interrupt service routine, clear the interrupt source,
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// the interrupt bit in the pending register, and restore the MASK register
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// to it's previous state.
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//
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// Addapt the core for fewer interrupt sources:
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// If less than 8 interrupt sources are required, than the 'is' parameter
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// can be set to the amount of required interrupts. Interrupts are mapped
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// starting at the LSBs. So only the 'is' LSBs per register are valid. All
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// other bits (i.e. the 8-'is' MSBs) are set to zero '0'.
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// Codesize is approximately linear to the amount of interrupts. I.e. using
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// 4 instead of 8 interrupt sources reduces the size by approx. half.
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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module simple_pic(
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clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, int_o,
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irq
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);
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parameter is = 8; // Number of interrupt sources
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//
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// Inputs & outputs
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//
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// 8bit WISHBONE bus slave interface
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input clk_i; // clock
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input rst_i; // reset (asynchronous active low)
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input cyc_i; // cycle
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input stb_i; // strobe (cycle and strobe are the same signal)
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input [ 2:1] adr_i; // address
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input we_i; // write enable
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input [ 7:0] dat_i; // data output
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output [ 7:0] dat_o; // data input
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output ack_o; // normal bus termination
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output int_o; // interrupt output
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//
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// Interrupt sources
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//
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input [is:1] irq; // interrupt request inputs
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//
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// Module body
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//
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reg [is:1] pol, edgen, pending, mask; // register bank
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reg [is:1] lirq, dirq; // latched irqs, delayed latched irqs
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//
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// perform parameter checks
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//
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// synopsys translate_off
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initial
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begin
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if(is > 8)
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$display("simple_pic: max. 8 interrupt sources supported.");
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end
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// synopsys translate_on
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//
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// latch interrupt inputs
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always @(posedge clk_i)
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lirq <= #1 irq;
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//
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// generate delayed latched irqs
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always @(posedge clk_i)
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dirq <= #1 lirq;
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//
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// generate actual triggers
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function trigger;
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input edgen, pol, lirq, dirq;
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reg edge_irq, level_irq;
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begin
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edge_irq = pol ? (lirq & ~dirq) : (dirq & ~lirq);
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level_irq = pol ? lirq : ~lirq;
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trigger = edgen ? edge_irq : level_irq;
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end
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endfunction
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reg [is:1] irq_event;
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integer n;
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always @(posedge clk_i)
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for(n=1; n<=is; n=n+1)
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irq_event[n] <= #1 trigger(edgen[n], pol[n], lirq[n], dirq[n]);
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//
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// generate wishbone register bank writes
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wire wb_acc = cyc_i & stb_i; // WISHBONE access
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wire wb_wr = wb_acc & we_i; // WISHBONE write access
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always @(posedge clk_i or negedge rst_i)
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if (~rst_i)
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begin
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pol <= #1 {{is}{1'b0}}; // clear polarity register
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edgen <= #1 {{is}{1'b0}}; // clear edge enable register
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mask <= #1 {{is}{1'b1}}; // mask all interrupts
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end
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else if(wb_wr) // wishbone write cycle??
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case (adr_i) // synopsys full_case parallel_case
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2'b00: edgen <= #1 dat_i[is-1:0]; // EDGE-ENABLE register
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2'b01: pol <= #1 dat_i[is-1:0]; // POLARITY register
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2'b10: mask <= #1 dat_i[is-1:0]; // MASK register
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2'b11: ; // PENDING register is a special case (see below)
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endcase
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// pending register is a special case
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always @(posedge clk_i or negedge rst_i)
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if (~rst_i)
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pending <= #1 {{is}{1'b0}}; // clear all pending interrupts
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else if ( wb_wr & (&adr_i) )
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pending <= #1 (pending & ~dat_i[is-1:0]) | irq_event;
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else
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pending <= #1 pending | irq_event;
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//
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// generate dat_o
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reg [7:0] dat_o;
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always @(posedge clk_i)
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case (adr_i) // synopsys full_case parallel_case
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2'b00: dat_o <= #1 { {{8-is}{1'b0}}, edgen};
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2'b01: dat_o <= #1 { {{8-is}{1'b0}}, pol};
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2'b10: dat_o <= #1 { {{8-is}{1'b0}}, mask};
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2'b11: dat_o <= #1 { {{8-is}{1'b0}}, pending};
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endcase
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//
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// generate ack_o
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reg ack_o;
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always @(posedge clk_i)
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ack_o <= #1 wb_acc & !ack_o;
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//
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// generate CPU interrupt signal
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reg int_o;
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always @(posedge clk_i)
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int_o <= #1 |(pending & ~mask);
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endmodule
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