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[/] [simple_spi/] [trunk/] [rtl/] [verilog/] [fifo4.v] - Blame information for rev 2

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/////////////////////////////////////////////////////////////////////
////                                                             ////
//// FIFO 4 entries deep                                         ////
////                                                             ////
//// Authors: Rudolf Usselmann, Richard Herveille                ////
////          rudi@asics.ws     richard@asics.ws                 ////
////                                                             ////
////                                                             ////
//// Download from: http://www.opencores.org/projects/sasc       ////
////                http://www.opencores.org/projects/simple_spi ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
////                                                             ////
//// Copyright (C) 2000-2002 Rudolf Usselmann, Richard Herveille ////
////                         www.asics.ws                        ////
////                         rudi@asics.ws, richard@asics.ws     ////
////                                                             ////
//// This source file may be used and distributed without        ////
//// restriction provided that this copyright statement is not   ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
////                                                             ////
////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
//// POSSIBILITY OF SUCH DAMAGE.                                 ////
////                                                             ////
/////////////////////////////////////////////////////////////////////
 
//  CVS Log
//
//  $Id: fifo4.v,v 1.1.1.1 2002-12-22 16:07:14 rherveille Exp $
//
//  $Date: 2002-12-22 16:07:14 $
//  $Revision: 1.1.1.1 $
//  $Author: rherveille $
//  $Locker:  $
//  $State: Exp $
//
// Change History:
//               $Log: not supported by cvs2svn $
//
 
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
 
 
// 4 entry deep fast fifo
module fifo4(clk, rst, clr,  din, we, dout, re, full, empty);
 
parameter dw = 8;
 
input           clk, rst;
input           clr;
input   [dw:1]  din;
input           we;
output  [dw:1]  dout;
input           re;
output          full, empty;
 
 
////////////////////////////////////////////////////////////////////
//
// Local Wires
//
 
reg     [dw:1]  mem[0:3];
reg     [1:0]   wp;
reg     [1:0]   rp;
wire    [1:0]   wp_p1;
wire    [1:0]   wp_p2;
wire    [1:0]   rp_p1;
wire            full, empty;
reg             gb;
 
////////////////////////////////////////////////////////////////////
//
// Misc Logic
//
 
always @(posedge clk or negedge rst)
        if(!rst)        wp <= #1 2'h0;
        else
        if(clr)         wp <= #1 2'h0;
        else
        if(we)          wp <= #1 wp_p1;
 
assign wp_p1 = wp + 2'h1;
assign wp_p2 = wp + 2'h2;
 
always @(posedge clk or negedge rst)
        if(!rst)        rp <= #1 2'h0;
        else
        if(clr)         rp <= #1 2'h0;
        else
        if(re)          rp <= #1 rp_p1;
 
assign rp_p1 = rp + 2'h1;
 
// Fifo Output
assign  dout = mem[ rp ];
 
// Fifo Input
always @(posedge clk)
        if(we)  mem[ wp ] <= #1 din;
 
// Status
assign empty = (wp == rp) & !gb;
assign full  = (wp == rp) &  gb;
 
// Guard Bit ...
always @(posedge clk)
        if(!rst)                        gb <= #1 1'b0;
        else
        if(clr)                         gb <= #1 1'b0;
        else
        if((wp_p1 == rp) & we)          gb <= #1 1'b1;
        else
        if(re)                          gb <= #1 1'b0;
 
endmodule

Line No.	Rev	Author	Line
1	2	rherveille	`/////////////////////////////////////////////////////////////////////`
2			`//// ////`
3			`//// FIFO 4 entries deep ////`
4			`//// ////`
5			`//// Authors: Rudolf Usselmann, Richard Herveille ////`
6			`//// rudi@asics.ws richard@asics.ws ////`
7			`//// ////`
8			`//// ////`
9			`//// Download from: http://www.opencores.org/projects/sasc ////`
10			`//// http://www.opencores.org/projects/simple_spi ////`
11			`//// ////`
12			`/////////////////////////////////////////////////////////////////////`
13			`//// ////`
14			`//// Copyright (C) 2000-2002 Rudolf Usselmann, Richard Herveille ////`
15			`//// www.asics.ws ////`
16			`//// rudi@asics.ws, richard@asics.ws ////`
17			`//// ////`
18			`//// This source file may be used and distributed without ////`
19			`//// restriction provided that this copyright statement is not ////`
20			`//// removed from the file and that any derivative work contains ////`
21			`//// the original copyright notice and the associated disclaimer.////`
22			`//// ////`
23			//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
24			`//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////`
25			`//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////`
26			`//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////`
27			`//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////`
28			`//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////`
29			`//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////`
30			`//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////`
31			`//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////`
32			`//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////`
33			`//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////`
34			`//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////`
35			`//// POSSIBILITY OF SUCH DAMAGE. ////`
36			`//// ////`
37			`/////////////////////////////////////////////////////////////////////`
38
39			`// CVS Log`
40			`//`
41			`// $Id: fifo4.v,v 1.1.1.1 2002-12-22 16:07:14 rherveille Exp $`
42			`//`
43			`// $Date: 2002-12-22 16:07:14 $`
44			`// $Revision: 1.1.1.1 $`
45			`// $Author: rherveille $`
46			`// $Locker: $`
47			`// $State: Exp $`
48			`//`
49			`// Change History:`
50			`// $Log: not supported by cvs2svn $`
51			`//`
52
53			`// synopsys translate_off`
54			`include "timescale.v"
55			`// synopsys translate_on`
56
57
58			`// 4 entry deep fast fifo`
59			`module fifo4(clk, rst, clr, din, we, dout, re, full, empty);`
60
61			`parameter dw = 8;`
62
63			`input clk, rst;`
64			`input clr;`
65			`input [dw:1] din;`
66			`input we;`
67			`output [dw:1] dout;`
68			`input re;`
69			`output full, empty;`
70
71
72			`////////////////////////////////////////////////////////////////////`
73			`//`
74			`// Local Wires`
75			`//`
76
77			`reg [dw:1] mem[0:3];`
78			`reg [1:0] wp;`
79			`reg [1:0] rp;`
80			`wire [1:0] wp_p1;`
81			`wire [1:0] wp_p2;`
82			`wire [1:0] rp_p1;`
83			`wire full, empty;`
84			`reg gb;`
85
86			`////////////////////////////////////////////////////////////////////`
87			`//`
88			`// Misc Logic`
89			`//`
90
91			`always @(posedge clk or negedge rst)`
92			`if(!rst) wp <= #1 2'h0;`
93			`else`
94			`if(clr) wp <= #1 2'h0;`
95			`else`
96			`if(we) wp <= #1 wp_p1;`
97
98			`assign wp_p1 = wp + 2'h1;`
99			`assign wp_p2 = wp + 2'h2;`
100
101			`always @(posedge clk or negedge rst)`
102			`if(!rst) rp <= #1 2'h0;`
103			`else`
104			`if(clr) rp <= #1 2'h0;`
105			`else`
106			`if(re) rp <= #1 rp_p1;`
107
108			`assign rp_p1 = rp + 2'h1;`
109
110			`// Fifo Output`
111			`assign dout = mem[ rp ];`
112
113			`// Fifo Input`
114			`always @(posedge clk)`
115			`if(we) mem[ wp ] <= #1 din;`
116
117			`// Status`
118			`assign empty = (wp == rp) & !gb;`
119			`assign full = (wp == rp) & gb;`
120
121			`// Guard Bit ...`
122			`always @(posedge clk)`
123			`if(!rst) gb <= #1 1'b0;`
124			`else`
125			`if(clr) gb <= #1 1'b0;`
126			`else`
127			`if((wp_p1 == rp) & we) gb <= #1 1'b1;`
128			`else`
129			`if(re) gb <= #1 1'b0;`
130
131			`endmodule`

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[/] [simple_spi/] [trunk/] [rtl/] [verilog/] [fifo4.v] - Blame information for rev 2