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[/] [simple_spi/] [trunk/] [rtl/] [verilog/] [fifo4.v] - Blame information for rev 2

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1 2 rherveille
/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// FIFO 4 entries deep                                         ////
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////                                                             ////
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//// Authors: Rudolf Usselmann, Richard Herveille                ////
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////          rudi@asics.ws     richard@asics.ws                 ////
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////                                                             ////
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////                                                             ////
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//// Download from: http://www.opencores.org/projects/sasc       ////
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////                http://www.opencores.org/projects/simple_spi ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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////                                                             ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann, Richard Herveille ////
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////                         www.asics.ws                        ////
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////                         rudi@asics.ws, richard@asics.ws     ////
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////                                                             ////
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//// This source file may be used and distributed without        ////
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//// restriction provided that this copyright statement is not   ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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////                                                             ////
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////     THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY     ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED   ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS   ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR      ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,         ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES    ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE   ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR        ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF  ////
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//// LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT  ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT  ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE         ////
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//// POSSIBILITY OF SUCH DAMAGE.                                 ////
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////                                                             ////
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/////////////////////////////////////////////////////////////////////
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//  CVS Log
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//
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//  $Id: fifo4.v,v 1.1.1.1 2002-12-22 16:07:14 rherveille Exp $
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//
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//  $Date: 2002-12-22 16:07:14 $
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//  $Revision: 1.1.1.1 $
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//  $Author: rherveille $
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//  $Locker:  $
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//  $State: Exp $
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//
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// Change History:
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//               $Log: not supported by cvs2svn $
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//
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// synopsys translate_off
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`include "timescale.v"
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// synopsys translate_on
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// 4 entry deep fast fifo
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module fifo4(clk, rst, clr,  din, we, dout, re, full, empty);
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parameter dw = 8;
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input           clk, rst;
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input           clr;
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input   [dw:1]  din;
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input           we;
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output  [dw:1]  dout;
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input           re;
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output          full, empty;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg     [dw:1]  mem[0:3];
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reg     [1:0]   wp;
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reg     [1:0]   rp;
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wire    [1:0]   wp_p1;
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wire    [1:0]   wp_p2;
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wire    [1:0]   rp_p1;
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wire            full, empty;
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reg             gb;
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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always @(posedge clk or negedge rst)
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        if(!rst)        wp <= #1 2'h0;
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        else
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        if(clr)         wp <= #1 2'h0;
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        else
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        if(we)          wp <= #1 wp_p1;
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assign wp_p1 = wp + 2'h1;
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assign wp_p2 = wp + 2'h2;
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always @(posedge clk or negedge rst)
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        if(!rst)        rp <= #1 2'h0;
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        else
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        if(clr)         rp <= #1 2'h0;
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        else
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        if(re)          rp <= #1 rp_p1;
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assign rp_p1 = rp + 2'h1;
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// Fifo Output
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assign  dout = mem[ rp ];
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// Fifo Input
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always @(posedge clk)
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        if(we)  mem[ wp ] <= #1 din;
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// Status
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assign empty = (wp == rp) & !gb;
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assign full  = (wp == rp) &  gb;
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// Guard Bit ...
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always @(posedge clk)
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        if(!rst)                        gb <= #1 1'b0;
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        else
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        if(clr)                         gb <= #1 1'b0;
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        else
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        if((wp_p1 == rp) & we)          gb <= #1 1'b1;
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        else
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        if(re)                          gb <= #1 1'b0;
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endmodule

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