Simple UART for FPGA is UART (Universal Asynchronous Receiver & Transmitter) controller for serial communication with an FPGA. The UART controller was implemented using VHDL 93 and is applicable to any FPGA.
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**Simple UART for FPGA requires: 1 start bit, 8 data bits, 1 stop bit!**
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The UART controller was simulated and tested in hardware.
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# Inputs and outputs ports:
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Port name | IN/OUT | Width | Port description
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---|:---:|:---:|---
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CLK | IN | 1b | System clock.
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RST | IN | 1b | High active synchronous reset.
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UART_TXD | OUT | 1b | Serial transmit data.
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UART_RXD | IN | 1b | Serial receive data.
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DATA_IN | IN | 8b | Data byte for transmit.
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DATA_SEND | IN | 1b | Send data byte for transmit.
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BUSY | OUT | 1b | Transmitter is busy, can not send next data.
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DATA_OUT | OUT | 8b | Received data byte.
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DATA_VLD | OUT | 1b | Received data byte is valid.
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FRAME_ERROR | OUT | 1b | Stop bit is invalid, current and next data may be corrupted.
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# Synthesis resource usage summary:
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Parity | LE (LUT) | FF | BRAM
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:---:|:---:|:---:|:---:
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none | 80 | 55 | 0
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even/odd | 91 | 58 | 0
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mark/space | 84 | 58 | 0
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*Synthesis was performed using Quartus II 64-Bit Version 13.0.1 for FPGA Altera Cyclone II with these settings: 115200 baud rate and 50 MHz system clock .*
