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mgeng |
//////////////////////////////////////////////////////////////////
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// //
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// The simu_mem project provides functional simulation models //
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// of commercially available RAMs. The following types are //
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// presently supported: //
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// //
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// - asynchronous static SRAMs //
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// - synchronous static RAMs ("Zero Bus Turnaround" RAM, ZBT //
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// RAM) //
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// //
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// Author(s): //
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// - Michael Geng (vhdl@MichaelGeng.de) //
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// //
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//////////////////////////////////////////////////////////////////
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// //
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// Copyright (C) 2008 Authors //
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// //
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// This source file may be used and distributed without //
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// restriction provided that this copyright statement is not //
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// removed from the file and that any derivative work contains //
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// the original copyright notice and the associated disclaimer. //
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// //
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// This source file is free software; you can redistribute it //
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// and/or modify it under the terms of the GNU Lesser General //
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// Public License as published by the Free Software Foundation; //
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// either version 2.1 of the License, or (at your option) any //
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// later version. //
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// //
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// This source is distributed in the hope that it will be //
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// useful, but WITHOUT ANY WARRANTY; without even the implied //
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// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
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// PURPOSE. See the GNU Lesser General Public License for more //
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// details. //
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// //
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// You should have received a copy of the GNU Lesser General //
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// Public License along with this source; if not, download it //
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// from http://www.opencores.org/lgpl.shtml //
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// //
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//////////////////////////////////////////////////////////////////
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//
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// CVS Revision History
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//
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// $Log: not supported by cvs2svn $
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Advantages of the simu_mem models
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=================================
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1. Consumes few simulator memory if only few memory
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locations are accessed because it internally uses a
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linked list.
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2. Simulates quickly because it does not contain timing
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information. Fast simulator startup time because of the
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linked list.
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3. Usable for any data and address bus width.
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4. Works at any clock frequency.
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5. Programmed in VHDL.
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When the simu_mem models will not be useful
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===========================================
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1. When it has to be synthesized.
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2. When a timing model is required. Ask your RAM vendor for
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a timing model.
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3. When your design is in Verilog.
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Where are the simulation models?
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================================
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The RAM simulation models are located in rtl/vhdl/. They were
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tested only with the Modelsim simulator.
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How were the models tested?
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===========================
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A testbench exists for ZBT RAMs. sim/rtl_sim/bin/sim.sh will execute
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the simulation. In order to run this test you must replace
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bench/verilog/samsung/k7n643645m_R03.v with the original simulation
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file from Samsung. You can find it on the Samsung semiconductor home
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page under High Speed SRAM / NtRAM / K7N643645M.
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