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---- ----
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---- Package used by the test pattern generator for the ----
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---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ----
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---- simulation model. ----
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---- ----
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---- This file is part of the simu_mem project. ----
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---- ----
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---- Authors: ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2008 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/lgpl.html ----
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---- ----
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----------------------------------------------------------------------
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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--
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LIBRARY ieee, misc;
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USE ieee.std_logic_1164.ALL;
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USE ieee.numeric_std.ALL;
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USE misc.math_pkg.ALL;
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PACKAGE patgen_pkg IS
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COMPONENT patgen IS
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GENERIC (
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clk_periode : TIME);
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port (
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Clk : IN STD_LOGIC;
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Rst : IN STD_LOGIC;
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Ena : IN STD_LOGIC;
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A : OUT STD_LOGIC_VECTOR;
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D : OUT STD_LOGIC_VECTOR;
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CKE_n : OUT STD_LOGIC;
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CS1_n : OUT STD_LOGIC;
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CS2 : OUT STD_LOGIC;
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CS2_n : OUT STD_LOGIC;
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WE_n : OUT STD_LOGIC;
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BW_n : OUT STD_LOGIC_VECTOR;
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OE_n : OUT STD_LOGIC;
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ADV : OUT STD_LOGIC;
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ZZ : OUT STD_LOGIC;
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LBO_n : OUT STD_LOGIC);
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END COMPONENT patgen;
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PROCEDURE random_vector (
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SIGNAL D : OUT STD_LOGIC_VECTOR;
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VARIABLE random : INOUT NATURAL);
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END PACKAGE patgen_pkg;
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PACKAGE BODY patgen_pkg IS
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PROCEDURE random_vector (
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SIGNAL D : OUT STD_LOGIC_VECTOR;
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VARIABLE random : INOUT NATURAL) IS
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BEGIN
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IF (D'length >= 31) THEN
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random := lcg (random);
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D (30 DOWNTO 0) <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(30 DOWNTO 0));
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random := lcg (random);
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D (D'length - 1 DOWNTO 31) <=
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STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D'length - 32 DOWNTO 0));
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else
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random := lcg (random);
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D <= STD_LOGIC_VECTOR (TO_UNSIGNED (random, 32)(D'length - 1 DOWNTO 0));
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END IF;
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END PROCEDURE random_vector;
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END PACKAGE BODY patgen_pkg;
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