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mgeng |
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---- ----
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---- Single port asynchronous static RAM simulation model ----
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---- ----
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---- This file is part of the simu_mem project ----
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---- ----
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---- Description ----
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---- This is a single port asynchronous memory. This files ----
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---- describes three architectures. Two architectures are ----
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---- traditional array based memories. One describes the memory ----
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---- as an array of STD_LOGIC_VECTOR, and the other describes ----
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---- the ARRAY as BIT_VECTOR. ----
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---- The third architecture describes the memory arranged as a ----
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---- linked list in order to conserve computer memory usage. The ----
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---- memory is organized as a linked list of BIT_VECTOR arrays ----
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---- whose size is defined by the constant PAGEDEPTH in ----
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---- single_port_pkg.vhd. Example for an applicable device: ----
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---- ----
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---- Manufacturer Device ----
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---- IDT IDT71V424 ----
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---- ----
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---- Advantages of this model: ----
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---- 1. User can choose between an array implementation (for ----
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---- applications which access almost all memory locations in ----
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---- on single simulation) or a linked list implementation ----
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---- which consumes only few simulator memory otherwise. ----
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---- 2. Simulates quickly because it does not contain timing ----
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---- information. Fast simulator startup time of the linked ----
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---- list model. ----
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---- 3. Usable for any data and address bus width. ----
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---- 4. Works at any clock frequency. ----
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---- 5. Programmed in VHDL. ----
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---- ----
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---- When this model will not be useful: ----
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---- 1. When it has to be synthesized. ----
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---- 2. When a timing model is required. Ask your RAM vendor for ----
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---- a timing model. ----
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---- 3. When your design is in Verilog. ----
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---- ----
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---- Authors: ----
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---- - Robert Paley, rpaley_yid@yahoo.com ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2005 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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--
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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--
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE work.linked_list_mem_pkg.ALL;
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ENTITY ASRAM IS
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PORT (
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D : IN STD_LOGIC_VECTOR; -- data in
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Q : OUT STD_LOGIC_VECTOR; -- data out
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A : IN STD_LOGIC_VECTOR; -- address bus
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CE_n : IN STD_LOGIC; -- not chip enable
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WE_n : IN STD_LOGIC; -- not write enable
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OE_n : IN STD_LOGIC; -- not output enable
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dealloc_mem : IN BOOLEAN := FALSE); -- control signal for deallocating memory,
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END ENTITY ASRAM;
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ARCHITECTURE array_mem_no_flag OF ASRAM IS
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BEGIN
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ASSERT D'LENGTH = Q'LENGTH
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REPORT "D and Q must have same the length"
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SEVERITY FAILURE;
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mem_proc : PROCESS (D, A, CE_n, WE_n, OE_n)
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TYPE mem_typ IS ARRAY (0 TO 2 ** A'length - 1) OF STD_LOGIC_VECTOR (D'RANGE);
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VARIABLE mem : mem_typ;
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BEGIN
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IF (CE_n = '0') AND (WE_n = '0') THEN -- Write
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mem (TO_INTEGER (unsigned (A))) := D;
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END IF;
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IF (CE_n = '0') AND (OE_n = '0') THEN -- Read
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Q <= mem (TO_INTEGER (unsigned (A)));
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ELSE
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Q <= (Q'RANGE => 'Z');
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END IF;
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END PROCESS mem_proc;
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END array_mem_no_flag;
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ARCHITECTURE array_mem OF ASRAM IS
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BEGIN
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ASSERT D'LENGTH = Q'LENGTH
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REPORT "D and Q must have same the length"
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SEVERITY FAILURE;
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mem_proc : PROCESS (D, A, CE_n, WE_n, OE_n)
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TYPE mem_typ IS ARRAY (0 TO 2 ** A'length - 1) OF BIT_VECTOR (D'RANGE);
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TYPE flag_typ IS ARRAY (0 TO 2 ** A'length - 1) OF BOOLEAN;
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VARIABLE mem : mem_typ;
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VARIABLE flag : flag_typ;
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BEGIN
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IF (CE_n = '0') AND (WE_n = '0') THEN -- Write
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mem (TO_INTEGER (unsigned (A))) := TO_BITVECTOR (D);
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flag (TO_INTEGER (unsigned (A))) := TRUE; -- set valid memory location flag
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END IF;
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IF (CE_n = '0') AND (OE_n = '0') THEN -- Read
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IF (flag (TO_INTEGER (unsigned (A))) = TRUE) THEN -- read data, either valid or 'U'
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Q <= TO_STDLOGICVECTOR (mem (TO_INTEGER (unsigned (A))));
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ELSE -- reading invalid memory location
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Q <= (Q'RANGE => 'U');
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END IF;
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ELSE
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Q <= (Q'RANGE => 'Z');
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END IF;
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END PROCESS mem_proc;
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END array_mem;
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ARCHITECTURE linked_list OF ASRAM IS
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BEGIN
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ASSERT D'LENGTH = Q'LENGTH
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REPORT "D and Q must have same the length"
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SEVERITY FAILURE;
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mem_proc : PROCESS (D, A, CE_n, WE_n, OE_n, dealloc_mem)
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VARIABLE mem_page_v : mem_page_ptr;
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VARIABLE D_v : STD_LOGIC_VECTOR (D'RANGE);
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VARIABLE A_v : NATURAL;
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BEGIN
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IF dealloc_mem THEN
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-- deallocate simulator memory
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deallocate_mem (mem_page_v);
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ELSE
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D_v := D;
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if (CE_n = '0') then
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A_v := TO_INTEGER (unsigned (A));
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end if;
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IF (CE_n = '0') AND (WE_n = '0') THEN -- Write
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rw_mem (data => D_v,
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addr => A_v,
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next_cell => mem_page_v,
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operation => write);
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END IF;
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IF (CE_n = '0') AND (OE_n = '0') THEN -- Read
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rw_mem (data => D_v,
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addr => A_v,
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next_cell => mem_page_v,
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operation => read);
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Q <= D_v;
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ELSE
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Q <= (D'RANGE => 'Z');
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END IF;
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END IF;
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END PROCESS mem_proc;
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END linked_list;
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