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mgeng |
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---- ----
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---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ----
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---- simulation model ----
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---- ----
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---- This file is part of the simu_mem project. ----
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---- ----
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---- Description ----
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---- This is a functional simulation model for single port ----
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---- synchronous static RAMs. Examples for applicable devices: ----
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---- ----
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---- Manufacturer Device ----
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---- Samsung K7N643645M ----
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---- ISSI IS61NLP51236 ----
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---- ----
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---- Advantages of this model: ----
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---- 1. Consumes few simulator memory if only few memory ----
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---- locations are accessed because it internally uses a ----
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---- linked list. ----
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---- 2. Simulates quickly because it does not contain timing ----
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---- information. Fast simulator startup time because of the ----
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---- linked list. ----
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---- 3. Usable for any data and address bus width. ----
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---- 4. Works at any clock frequency. ----
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---- 5. Programmed in VHDL. ----
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---- ----
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---- When this model will not be useful: ----
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---- 1. When it has to be synthesized. ----
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---- 2. When a timing model is required. Ask your RAM vendor for ----
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---- a timing model. ----
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---- 3. When all memory locations have to be accessed in one ----
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---- single simulation run. The linked list model will not ----
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---- be well suited then. ----
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---- 4. When your design is in Verilog. ----
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---- ----
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---- For above reasons a typical application is a functional ----
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---- simulation of a design which uses external synchronous ----
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---- static RAMs. ----
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---- ----
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---- Authors: ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2008 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.gnu.org/licenses/lgpl.html ----
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---- ----
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----------------------------------------------------------------------
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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--
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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USE work.ZBT_RAM_pkg.ALL;
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USE work.linked_list_mem_pkg.ALL;
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ENTITY ZBT_RAM IS
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GENERIC (
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debug : INTEGER := 0); -- >= 1: print write operations
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-- >= 2: print also read operations
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PORT (
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Clk : IN STD_LOGIC;
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D : IN STD_LOGIC_VECTOR;
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Q : OUT STD_LOGIC_VECTOR;
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A : IN STD_LOGIC_VECTOR;
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CKE_n : IN STD_LOGIC;
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CS1_n : IN STD_LOGIC;
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CS2 : IN STD_LOGIC;
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CS2_n : IN STD_LOGIC;
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WE_n : IN STD_LOGIC;
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BW_n : IN STD_LOGIC_VECTOR;
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OE_n : IN STD_LOGIC;
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ADV : IN STD_LOGIC;
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ZZ : IN STD_LOGIC;
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LBO_n : IN STD_LOGIC;
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dealloc_mem : IN BOOLEAN := FALSE); -- control SIGNAL for deallocating memory
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END ENTITY ZBT_RAM;
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ARCHITECTURE LinkedList OF ZBT_RAM IS
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CONSTANT D_width : INTEGER := D'LENGTH;
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CONSTANT A_width : INTEGER := A'LENGTH;
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TYPE mem_page_ptr_array IS ARRAY (0 TO D_width / 9 - 1) of mem_page_ptr;
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SIGNAL state, last_state : state_type := Deselect;
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SIGNAL operation : state_type := Deselect;
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SIGNAL DOut : STD_LOGIC_VECTOR (D_width - 1 DOWNTO 0) := (OTHERS => 'Z');
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SIGNAL A_delayed_1 : NATURAL;
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SIGNAL A_delayed_2 : NATURAL;
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SIGNAL BW_n_delayed_1 : STD_LOGIC_VECTOR (D_width / 9 - 1 DOWNTO 0);
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SIGNAL BW_n_delayed_2 : STD_LOGIC_VECTOR (D_width / 9 - 1 DOWNTO 0);
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SIGNAL ADV_delayed : STD_LOGIC;
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SIGNAL sleep_count : INTEGER RANGE 4 DOWNTO 0 := 0;
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BEGIN
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ASSERT BW_n'LENGTH = D'LENGTH / 9
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REPORT "Error: BW_n'length must be equal to D'length / 9"
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SEVERITY FAILURE;
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mem_proc : PROCESS (Clk, dealloc_mem) IS
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VARIABLE state_v : state_type;
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VARIABLE mem_page_v : mem_page_ptr_array;
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VARIABLE D_v : STD_LOGIC_VECTOR (8 DOWNTO 0);
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BEGIN
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IF dealloc_mem THEN
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FOR i IN 0 TO D_width / 9 - 1 LOOP
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deallocate_mem (mem_page_v (i));
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END LOOP;
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ELSIF rising_edge (Clk) THEN
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IF (CKE_n = '0') THEN
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state_v := calc_state (CS1_n, CS2, CS2_n, WE_n, BW_n, OE_n, ADV, ZZ, operation);
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operation <= calc_operation (state_v, operation);
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IF ((state_v = read) OR (state_v = dummy_read) OR (state_v = write)) THEN
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A_delayed_1 <= to_INTEGER (UNSIGNED (A));
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END IF;
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IF ((state_v = write) OR (state_v = write_continue)) THEN
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BW_n_delayed_1 <= BW_n;
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END IF;
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IF (state_v = invalid_state) THEN
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REPORT "Invalid state" SEVERITY ERROR;
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END IF;
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state <= state_v;
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last_state <= state;
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ADV_delayed <= ADV;
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BW_n_delayed_2 <= BW_n_delayed_1;
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END IF;
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IF (ZZ = '1') THEN
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sleep_count <= 4;
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ELSIF (sleep_count > 0) THEN
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sleep_count <= sleep_count - 1;
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END IF;
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IF (sleep_count = 0) THEN
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IF (((state = write) OR
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(state = read) OR
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(state = dummy_read) OR
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(state = write_abort)) AND (CKE_n = '0')) THEN
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A_delayed_2 <= A_delayed_1;
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ELSIF (ADV_delayed = '1') AND (CKE_n = '0') THEN
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mgeng |
IF (A_delayed_2 MOD 4 < 3) THEN
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A_delayed_2 <= A_delayed_2 + 1;
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ELSE
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A_delayed_2 <= A_delayed_1;
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END IF;
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END IF;
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IF ((CKE_n = '0') AND (BW_n_delayed_2 /= (D_width / 9 - 1 DOWNTO 0 => '1')) AND
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((last_state = write) OR (last_state = write_continue))) THEN
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FOR i IN 0 TO D_width / 9 - 1 LOOP
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IF (BW_n_delayed_2 (i) = '0') THEN
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D_v := D (9 * (i + 1) - 1 DOWNTO 9 * i);
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rw_mem (data => D_v,
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addr => A_delayed_2,
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next_cell => mem_page_v (i),
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operation => write);
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IF (Debug >= 1) THEN
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REPORT ("DBG, " & TIME'IMAGE (now) & ": Write " &
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INTEGER'IMAGE (to_INTEGER (UNSIGNED (D_v))) & " to address=" &
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INTEGER'IMAGE (A_delayed_2) & ", bank=" & INTEGER'IMAGE (i));
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END IF;
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END IF;
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END LOOP;
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END IF;
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ELSIF (sleep_count = 3) THEN
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A_delayed_2 <= 0;
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END IF;
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END IF;
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IF falling_edge (Clk) THEN
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IF (sleep_count = 0) THEN
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IF (CKE_n = '0') THEN
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IF ((last_state = read) OR (last_state = read_continue) OR
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(last_state = dummy_read) OR (last_state = dummy_read_continue)) THEN
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FOR i IN 0 TO D_width / 9 - 1 LOOP
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rw_mem (data => D_v,
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addr => A_delayed_2,
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next_cell => mem_page_v (i),
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operation => read);
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DOut (9 * (i + 1) - 1 DOWNTO 9 * i) <= D_v;
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IF (Debug >= 2) THEN
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REPORT ("DBG, " & TIME'IMAGE (now) & ": Read " &
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INTEGER'IMAGE (to_INTEGER (UNSIGNED (D_v))) & " from address=" &
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INTEGER'IMAGE (A_delayed_2) & ", bank=" & INTEGER'IMAGE (i));
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END IF;
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END LOOP;
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ELSE
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DOut <= (OTHERS => 'Z');
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END IF;
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END IF;
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ELSE
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DOut <= (OTHERS => 'Z');
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END IF;
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END IF;
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END PROCESS mem_proc;
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Q <= (Q'RANGE => 'Z') WHEN (OE_n = '1') ELSE DOut;
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END LinkedList;
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