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mgeng |
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---- ----
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---- Synchronous static RAM ("Zero Bus Turnaround" RAM, ZBT RAM) ----
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---- simulation model ----
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---- ----
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---- This file is part of the simu_mem project ----
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---- ----
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---- Description ----
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---- State definition and next state calculation function for ----
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---- the ZBT RAM model ----
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---- ----
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---- Authors: ----
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---- - Michael Geng, vhdl@MichaelGeng.de ----
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---- ----
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----------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2008 Authors ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer. ----
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---- ----
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---- This source file is free software; you can redistribute it ----
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---- and/or modify it under the terms of the GNU Lesser General ----
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---- Public License as published by the Free Software Foundation; ----
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---- either version 2.1 of the License, or (at your option) any ----
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---- later version. ----
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---- ----
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---- This source is distributed in the hope that it will be ----
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---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
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---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
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---- PURPOSE. See the GNU Lesser General Public License for more ----
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---- details. ----
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---- ----
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---- You should have received a copy of the GNU Lesser General ----
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---- Public License along with this source; if not, download it ----
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---- from http://www.opencores.org/lgpl.shtml ----
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---- ----
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----------------------------------------------------------------------
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-- CVS Revision History
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--
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-- $Log: not supported by cvs2svn $
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--
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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PACKAGE ZBT_RAM_pkg IS
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TYPE state_type IS (
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sleep,
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deselect,
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deselect_continue,
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read,
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read_continue,
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dummy_read,
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dummy_read_continue,
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write,
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write_continue,
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write_abort,
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write_abort_continue,
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invalid_state);
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FUNCTION calc_state (
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CS1_n : STD_LOGIC;
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CS2 : STD_LOGIC;
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CS2_n : STD_LOGIC;
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WE_n : STD_LOGIC;
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BW_n : STD_LOGIC_VECTOR;
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OE_n : STD_LOGIC;
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ADV : STD_LOGIC;
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ZZ : STD_LOGIC;
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operation : state_type) RETURN state_type;
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FUNCTION calc_operation (
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state : state_type;
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operation : state_type) RETURN state_type;
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END PACKAGE ZBT_RAM_pkg;
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PACKAGE BODY ZBT_RAM_pkg IS
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FUNCTION calc_state (
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CS1_n : STD_LOGIC;
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CS2 : STD_LOGIC;
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CS2_n : STD_LOGIC;
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WE_n : STD_LOGIC;
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BW_n : STD_LOGIC_VECTOR;
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OE_n : STD_LOGIC;
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ADV : STD_LOGIC;
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ZZ : STD_LOGIC;
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operation : state_type) RETURN state_type IS
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VARIABLE selected : BOOLEAN;
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BEGIN
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selected := ((CS1_n = '0') AND (CS2 = '1') AND (CS2_n = '0'));
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IF (ZZ = '1') THEN
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RETURN sleep;
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ELSIF ((ADV = '0') AND (NOT selected)) THEN
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RETURN deselect;
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ELSIF ((ADV = '1') AND (operation = deselect)) THEN
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RETURN deselect_continue;
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ELSIF (selected AND (ADV = '0') AND (WE_n = '1') AND (OE_n = '0')) THEN
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RETURN read;
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ELSIF ((ADV = '1') AND (OE_n = '0') AND (operation = Read)) THEN
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RETURN read_continue;
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ELSIF (selected AND (ADV = '0') AND (WE_n = '1') AND (OE_n = '1')) THEN
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RETURN dummy_read;
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ELSIF ((ADV = '1') AND (OE_n = '1') AND (operation = Read)) THEN
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RETURN dummy_read_continue;
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ELSIF (selected AND (ADV = '0') AND (WE_n = '0') AND (BW_n /= (BW_n'range => '1'))) THEN
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RETURN write;
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ELSIF ((ADV = '1') AND (BW_n /= (BW_n'range => '1')) AND (operation = write)) THEN
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RETURN write_continue;
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ELSIF (selected AND (ADV = '0') AND (WE_n = '0') AND (BW_n = (BW_n'range => '1')) AND
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(operation = Write)) THEN
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RETURN write_abort;
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ELSIF ((ADV = '1') AND (BW_n = (BW_n'range => '1')) AND (operation = write_abort)) THEN
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RETURN write_abort_continue;
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ELSE
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RETURN invalid_state;
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END IF;
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END FUNCTION calc_state;
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FUNCTION calc_operation (
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state : state_type;
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operation : state_type) RETURN state_type IS
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BEGIN
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CASE state IS
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WHEN deselect | write | write_abort | read =>
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RETURN state;
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WHEN dummy_read =>
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RETURN read;
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WHEN OTHERS =>
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RETURN operation;
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END CASE;
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END FUNCTION calc_operation;
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END PACKAGE BODY ZBT_RAM_pkg;
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