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[/] [sincos/] [trunk/] [vhdl/] [msi/] [pipestage/] [pipestage.vhd] - Blame information for rev 13

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----------------------------------------------------------------------------------------------------
-- (c) 2005-2010 Hoffmann RF & DSP    opencores@hoffmann-hochfrequenz.de
-- V1.0   2010-nov-22  published under BSD license.
----------------------------------------------------------------------------------------------------
-- Design Name:  pipestage.vhd
-- Description:         pipeline stage with variable width and depth
--
-- The length of the pipeline must be known at compile time and
-- be passed as a generic. 
-- The width is taken from the connected busses if needed.
-- There are several flavours of pipestages depending on the
-- type of the signal to be delayed. 
--
-- If n_stages = 0, clk and ce are ignored, of course.
-- If you want to use Xilinx SRL16 or 32, do not use rst.
--
-- calls other entities and libs: only ieee standard
--
----------------------------------------------------------------------------------------------------
 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity slv_pipestage is
  generic (
    n_stages: natural  := 1
  );
  Port (
    clk: in  std_logic;
    ce:  in  std_logic := '1';
    rst: in  std_logic := '0';
 
    i:   in  std_logic_vector;
    o:   out std_logic_vector
    );
end slv_pipestage;
 
 
architecture rtl of slv_pipestage is
 
 
-- copy a std_logic value to all locations of a variable size std_logic_vector.
function blow_up(b: std_logic; s: integer) return std_logic_vector is
  variable r: std_logic_vector(s-1 downto 0);
begin
  for n in 0 to s-1 loop
    r(n) := b;
  end loop;
  return r;
end;
 
 
 
begin
 
assert i'length = o'length
  report "slv_pipestage: input and output length do not match: "
       & integer'image(i'length)
       & " vs. "
       & integer'image(o'length)
  severity error;
 
 
ns0: if n_stages = 0
generate
begin
  o <= i;
end generate;
 
 
ns1: if n_stages = 1
generate
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
        o <= blow_up('0', o'length);
      elsif ce = '1'
      then
        o <= i;
      end if;
    end if; -- rising_edge()
  end process;
end generate;
 
 
 
ns2: if n_stages >= 2
generate
  type bla is array(0 to n_stages-1) of  std_logic_vector(i'range);
        signal reg: bla;
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
        for n in reg'range loop
          reg(n) <= blow_up('0', o'length); -- other doesn't work here :-(
                          end loop;
      elsif ce = '1'
      then
        reg(0) <= i;
                                for n in 1 to n_stages-1 loop
                                        reg(n) <= reg(n-1);
                                end loop;
       end if;
    end if; -- rising_edge()
  end process;
  o <= reg(n_stages-1);
end generate;
 
end rtl;
 
----------------------------------------------------------------------------------------------------
 
-- the rest is mostly copy & paste.
 
----------------------------------------------------------------------------------------------------
-- std_logic version
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
entity sl_pipestage is
  generic (
    n_stages: natural  := 1
  );
  Port (
    clk: in  std_logic;
    ce:  in  std_logic := '1';
    rst: in  std_logic := '0';
 
    i:   in  std_logic;
    o:   out std_logic
    );
end sl_pipestage;
 
 
architecture rtl of sl_pipestage is
 
begin
 
ns0: if n_stages = 0
generate
begin
  o <= i;
end generate;
 
 
ns1: if n_stages = 1
generate
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
        o <= '0';
      elsif ce = '1'
      then
        o <= i;
      end if;
    end if; -- rising_edge()
  end process;
end generate;
 
 
 
ns2: if n_stages >= 2
generate
  type bla is array(0 to n_stages-1) of  std_logic;
        signal reg: bla;
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
                  for n in reg'range loop
          reg(n) <= '0';
                          end loop;
      elsif ce = '1'
      then
        reg(0) <= i;
                                for n in 1 to n_stages-1 loop
                                        reg(n) <= reg(n-1);
                                end loop;
       end if;
    end if; -- rising_edge()
  end process;
  o <= reg(n_stages-1);
end generate;
 
end rtl;
 
 
 
 
----------------------------------------------------------------------------------------------------
-- boolean version
--
-- boolean, integer and float are unresolved types. 
-- Modelsim warns for these about potential multisource assignments.
-- This is harmless. n_stages is still unknown when the architecture is compiled.
-- Nevertheless the compiler could see that whatever n_stages might be,
-- it cannot be 1 AND 2 at the same time.
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
entity bool_pipestage is
  generic (
    n_stages: natural  := 1
  );
  Port (
    clk: in  std_logic;
    ce:  in  std_logic := '1';
    rst: in  std_logic;
 
    i:   in  boolean;
    o:   out boolean
  );
end bool_pipestage;
 
 
 
architecture rtl of bool_pipestage is
 
begin
 
ns0: if n_stages = 0
generate
begin
  o <= i;
end generate;
 
 
ns1: if n_stages = 1
generate
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
        o <= false;
      elsif ce = '1'
      then
        o <= i;
      end if;
    end if; -- rising_edge()
  end process;
end generate;
 
 
ns2: if n_stages >= 2
generate
  type bla is array(0 to n_stages-1) of  boolean;
        signal reg: bla;
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
                  for n in reg'range loop
          reg(n) <= false;
                          end loop;
      elsif ce = '1'
      then
        reg(0) <= i;
                                for n in 1 to n_stages-1 loop
                                        reg(n) <= reg(n-1);
                                end loop;
       end if;
    end if; -- rising_edge()
  end process;
  o <= reg(n_stages-1);
end generate;
 
end rtl;
 
 
 
----------------------------------------------------------------------------------------------------
-- signed version
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
entity signed_pipestage is
  generic (
    n_stages: natural  := 1
  );
  Port (
    clk: in  std_logic;
    ce:  in  std_logic := '1';
    rst: in  std_logic := '0';
 
    i:   in  signed;
    o:   out signed
  );
end signed_pipestage;
 
 
architecture rtl of signed_pipestage is
 
 
function blow_up(b: std_logic; s: integer) return signed is
  variable r: signed(s-1 downto 0);
begin
  for n in 0 to s-1 loop
    r(n) := b;
  end loop;
  return r;
end;
 
 
begin
 
assert i'length = o'length
  report "signed_pipestage: input and output length do not match: "
       & integer'image(i'length)
       & " vs. "
       & integer'image(o'length)
  severity error;
 
 
ns0: if n_stages = 0
generate
begin
  o <= i;
end generate;
 
 
ns1: if n_stages = 1
generate
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
        o <= blow_up('0', o'length);
      elsif ce = '1'
      then
        o <= i;
      end if;
    end if; -- rising_edge()
  end process;
end generate;
 
 
 
ns2: if n_stages >= 2
generate
  type bla is array(0 to n_stages-1) of  signed(i'range);
        signal reg: bla;
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
                  for n in reg'range loop
          reg(n) <= blow_up('0', o'length);
                          end loop;
      elsif ce = '1'
      then
        reg(0) <= i;
                                for n in 1 to n_stages-1 loop
                                        reg(n) <= reg(n-1);
                                end loop;
       end if;
    end if; -- rising_edge()
  end process;
  o <= reg(n_stages-1);
end generate;
 
end rtl;
 
----------------------------------------------------------------------------------------------------
-- unsigned version
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
entity unsigned_pipestage is
  generic (
    n_stages: natural  := 1     -- 0 to quite a few
  );
  Port (
    clk: in  std_logic;
    ce:  in  std_logic := '1';
    rst: in  std_logic := '0';
 
    i:   in  unsigned;
    o:   out unsigned
  );
end unsigned_pipestage;
 
 
 
architecture rtl of unsigned_pipestage is
 
 
function blow_up(b: std_logic; s: integer) return unsigned is
  variable r: unsigned(s-1 downto 0);
begin
  for n in 0 to s-1 loop
    r(n) := b;
  end loop;
  return r;
end;
 
 
begin
 
assert i'length = o'length
  report "unsigned_pipestage: input and output length do not match: "
       & integer'image(i'length)
       & " vs. "
       & integer'image(o'length)
  severity error;
 
 
ns0: if n_stages = 0
generate
begin
  o <= i;
end generate;
 
 
ns1: if n_stages = 1
generate
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
        o <= blow_up('0', o'length);
      elsif ce = '1'
      then
        o <= i;
      end if;
    end if; -- rising_edge()
  end process;
end generate;
 
 
 
ns2: if n_stages >= 2
generate
  type bla is array(0 to n_stages-1) of  unsigned(i'range);
        signal reg: bla;
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
                  for n in reg'range loop
          reg(n) <= blow_up('0', o'length);
                          end loop;
      elsif ce = '1'
      then
        reg(0) <= i;
                                for n in 1 to n_stages-1 loop
                                        reg(n) <= reg(n-1);
                                end loop;
       end if;
    end if; -- rising_edge()
  end process;
  o <= reg(n_stages-1);
end generate;
 
end rtl;
 
 
----------------------------------------------------------------------------------------------------
-- integer version
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
entity integer_pipestage is
  generic (
    n_stages: natural  := 1
  );
  Port (
    clk: in  std_logic;
    ce:  in  std_logic := '1';
    rst: in  std_logic := '0';
 
    i:   in  integer;
    o:   out integer
  );
end integer_pipestage;
 
 
architecture rtl of integer_pipestage is
 
begin
 
ns0: if n_stages = 0
generate
begin
  o <= i;
end generate;
 
 
ns1: if n_stages = 1
generate
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
        o <= 0;
      elsif ce = '1'
      then
        o <= i;
      end if;
    end if; -- rising_edge()
  end process;
end generate;
 
 
ns2: if n_stages >= 2
generate
  type bla is array(0 to n_stages-1) of  integer;
        signal reg: bla;
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
                  for n in reg'range loop
          reg(n) <= 0;
                          end loop;
      elsif ce = '1'
      then
        reg(0) <= i;
                                for n in 1 to n_stages-1 loop
                                        reg(n) <= reg(n-1);
                                end loop;
       end if;
    end if; -- rising_edge()
  end process;
  o <= reg(n_stages-1);
end generate;
 
end rtl;
 
 
----------------------------------------------------------------------------------------------------
-- real version
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
entity real_pipestage is
  generic (
    n_stages: natural  := 1
  );
  Port (
    clk: in  std_logic;
    ce:  in  std_logic := '1';
    rst: in  std_logic := '0';
 
    i:   in  real;
    o:   out real
  );
end real_pipestage;
 
 
 
 
architecture rtl of real_pipestage is
 
begin
 
ns0: if n_stages = 0
generate
begin
  o <= i;
end generate;
 
 
ns1: if n_stages = 1
generate
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
        o <= 0.0;
      elsif ce = '1'
      then
        o <= i;
      end if;
    end if; -- rising_edge()
  end process;
end generate;
 
 
ns2: if n_stages >= 2
generate
  type bla is array(0 to n_stages-1) of  real;
        signal reg: bla;
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
                  for n in reg'range loop
          reg(n) <= 0.0;
                          end loop;
      elsif ce = '1'
      then
        reg(0) <= i;
                                for n in 1 to n_stages-1 loop
                                        reg(n) <= reg(n-1);
                                end loop;
       end if;
    end if; -- rising_edge()
  end process;
  o <= reg(n_stages-1);
end generate;
 
end rtl;
 
 
 
 
--------------------------------------------------------------------------------------------------
-- unsigned fixed point version
--
-- If you don't have / cannot compile the floatfixlib, comment out the rest of the file.
-- David Bishop's version as supplied with Modelsim 6.5 seems to work with ISE 12.3, too.
--
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library floatfixlib;
use floatfixlib.fixed_pkg.all;
 
entity ufixed_pipestage is
  generic (
    n_stages: natural  := 1
  );
  Port (
    clk: in  std_logic;
    ce:  in  std_logic := '1';
    rst: in  std_logic := '0';
 
    i:   in  ufixed;
    o:   out ufixed
  );
end ufixed_pipestage;
 
 
 
architecture rtl of ufixed_pipestage is
 
 
function blow_up(b: std_logic; s: integer) return ufixed is
  variable r: ufixed(s-1 downto 0);
begin
  for n in 0 to s-1 loop
    r(n) := b;
  end loop;
  return r;
end;
 
 
begin
 
assert i'length = o'length
  report "ufixed_pipestage: input and output length do not match: "
       & integer'image(i'length)
       & " vs. "
       & integer'image(o'length)
  severity error;
 
 
ns0: if n_stages = 0
generate
begin
  o <= i;
end generate;
 
 
ns1: if n_stages = 1
generate
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
        o <= blow_up('0', o'length);
      elsif ce = '1'
      then
        o <= i;
      end if;
    end if; -- rising_edge()
  end process;
end generate;
 
 
 
ns2: if n_stages >= 2
generate
  type bla is array(0 to n_stages-1) of  ufixed(i'range);
        signal reg: bla;
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
                  for n in reg'range loop
          reg(n) <= blow_up('0', o'length);
                          end loop;
      elsif ce = '1'
      then
        reg(0) <= i;
                                for n in 1 to n_stages-1 loop
                                        reg(n) <= reg(n-1);
                                end loop;
       end if;
    end if; -- rising_edge()
  end process;
  o <= reg(n_stages-1);
end generate;
 
end rtl;
 
 
 
----------------------------------------------------------------------------------------------------
-- signed fixed point version
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
library floatfixlib;
use floatfixlib.fixed_pkg.all;
 
entity sfixed_pipestage is
  generic (
    n_stages: natural  := 1
  );
  Port (
    clk: in  std_logic;
    ce:  in  std_logic := '1';
    rst: in  std_logic := '0';
 
    i:   in  sfixed;
    o:   out sfixed
  );
end sfixed_pipestage;
 
 
 
architecture rtl of sfixed_pipestage is
 
 
function blow_up(b: std_logic; s: integer) return sfixed is
  variable r: sfixed(s-1 downto 0);
begin
  for n in 0 to s-1 loop
    r(n) := b;
  end loop;
  return r;
end;
 
 
begin
 
assert i'length = o'length
  report "sfixed_pipestage: input and output length do not match: "
       & integer'image(i'length)
       & " vs. "
       & integer'image(o'length)
  severity error;
 
 
ns0: if n_stages = 0
generate
begin
  o <= i;
end generate;
 
 
ns1: if n_stages = 1
generate
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
        o <= blow_up('0', o'length);
      elsif ce = '1'
      then
        o <= i;
      end if;
    end if; -- rising_edge()
  end process;
end generate;
 
 
 
ns2: if n_stages >= 2
generate
  type bla is array(0 to n_stages-1) of  sfixed(i'range);
        signal reg: bla;
begin
  u_reg: process(clk)
  begin
    if rising_edge(clk)
    then
      if rst = '1'
      then
                  for n in reg'range loop
          reg(n) <= blow_up('0', o'length);
                          end loop;
      elsif ce = '1'
      then
        reg(0) <= i;
                                for n in 1 to n_stages-1 loop
                                        reg(n) <= reg(n-1);
                                end loop;
       end if;
    end if; -- rising_edge()
  end process;
  o <= reg(n_stages-1);
end generate;
 
end rtl;
 

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Subversion Repositories sincos

[/] [sincos/] [trunk/] [vhdl/] [msi/] [pipestage/] [pipestage.vhd] - Blame information for rev 13

Line No.	Rev	Author	Line
1	13	dk4xp	`----------------------------------------------------------------------------------------------------`
2			`-- (c) 2005-2010 Hoffmann RF & DSP opencores@hoffmann-hochfrequenz.de`
3			`-- V1.0 2010-nov-22 published under BSD license.`
4			`----------------------------------------------------------------------------------------------------`
5			`-- Design Name: pipestage.vhd`
6			`-- Description: pipeline stage with variable width and depth`
7			`--`
8			`-- The length of the pipeline must be known at compile time and`
9			`-- be passed as a generic.`
10			`-- The width is taken from the connected busses if needed.`
11			`-- There are several flavours of pipestages depending on the`
12			`-- type of the signal to be delayed.`
13			`--`
14			`-- If n_stages = 0, clk and ce are ignored, of course.`
15			`-- If you want to use Xilinx SRL16 or 32, do not use rst.`
16			`--`
17			`-- calls other entities and libs: only ieee standard`
18			`--`
19			`----------------------------------------------------------------------------------------------------`
20
21			`library ieee;`
22			`use ieee.std_logic_1164.all;`
23			`use ieee.numeric_std.all;`
24
25			`entity slv_pipestage is`
26			`generic (`
27			`n_stages: natural := 1`
28			`);`
29			`Port (`
30			`clk: in std_logic;`
31			`ce: in std_logic := '1';`
32			`rst: in std_logic := '0';`
33
34			`i: in std_logic_vector;`
35			`o: out std_logic_vector`
36			`);`
37			`end slv_pipestage;`
38
39
40			`architecture rtl of slv_pipestage is`
41
42
43			`-- copy a std_logic value to all locations of a variable size std_logic_vector.`
44			`function blow_up(b: std_logic; s: integer) return std_logic_vector is`
45			`variable r: std_logic_vector(s-1 downto 0);`
46			`begin`
47			`for n in 0 to s-1 loop`
48			`r(n) := b;`
49			`end loop;`
50			`return r;`
51			`end;`
52
53
54
55			`begin`
56
57			`assert i'length = o'length`
58			`report "slv_pipestage: input and output length do not match: "`
59			`& integer'image(i'length)`
60			`& " vs. "`
61			`& integer'image(o'length)`
62			`severity error;`
63
64
65			`ns0: if n_stages = 0`
66			`generate`
67			`begin`
68			`o <= i;`
69			`end generate;`
70
71
72			`ns1: if n_stages = 1`
73			`generate`
74			`begin`
75			`u_reg: process(clk)`
76			`begin`
77			`if rising_edge(clk)`
78			`then`
79			`if rst = '1'`
80			`then`
81			`o <= blow_up('0', o'length);`
82			`elsif ce = '1'`
83			`then`
84			`o <= i;`
85			`end if;`
86			`end if; -- rising_edge()`
87			`end process;`
88			`end generate;`
89
90
91
92			`ns2: if n_stages >= 2`
93			`generate`
94			`type bla is array(0 to n_stages-1) of std_logic_vector(i'range);`
95			`signal reg: bla;`
96			`begin`
97			`u_reg: process(clk)`
98			`begin`
99			`if rising_edge(clk)`
100			`then`
101			`if rst = '1'`
102			`then`
103			`for n in reg'range loop`
104			`reg(n) <= blow_up('0', o'length); -- other doesn't work here :-(`
105			`end loop;`
106			`elsif ce = '1'`
107			`then`
108			`reg(0) <= i;`
109			`for n in 1 to n_stages-1 loop`
110			`reg(n) <= reg(n-1);`
111			`end loop;`
112			`end if;`
113			`end if; -- rising_edge()`
114			`end process;`
115			`o <= reg(n_stages-1);`
116			`end generate;`
117
118			`end rtl;`
119
120			`----------------------------------------------------------------------------------------------------`
121
122			`-- the rest is mostly copy & paste.`
123
124			`----------------------------------------------------------------------------------------------------`
125			`-- std_logic version`
126
127			`library IEEE;`
128			`use IEEE.STD_LOGIC_1164.ALL;`
129			`use IEEE.numeric_std.all;`
130
131			`entity sl_pipestage is`
132			`generic (`
133			`n_stages: natural := 1`
134			`);`
135			`Port (`
136			`clk: in std_logic;`
137			`ce: in std_logic := '1';`
138			`rst: in std_logic := '0';`
139
140			`i: in std_logic;`
141			`o: out std_logic`
142			`);`
143			`end sl_pipestage;`
144
145
146			`architecture rtl of sl_pipestage is`
147
148			`begin`
149
150			`ns0: if n_stages = 0`
151			`generate`
152			`begin`
153			`o <= i;`
154			`end generate;`
155
156
157			`ns1: if n_stages = 1`
158			`generate`
159			`begin`
160			`u_reg: process(clk)`
161			`begin`
162			`if rising_edge(clk)`
163			`then`
164			`if rst = '1'`
165			`then`
166			`o <= '0';`
167			`elsif ce = '1'`
168			`then`
169			`o <= i;`
170			`end if;`
171			`end if; -- rising_edge()`
172			`end process;`
173			`end generate;`
174
175
176
177			`ns2: if n_stages >= 2`
178			`generate`
179			`type bla is array(0 to n_stages-1) of std_logic;`
180			`signal reg: bla;`
181			`begin`
182			`u_reg: process(clk)`
183			`begin`
184			`if rising_edge(clk)`
185			`then`
186			`if rst = '1'`
187			`then`
188			`for n in reg'range loop`
189			`reg(n) <= '0';`
190			`end loop;`
191			`elsif ce = '1'`
192			`then`
193			`reg(0) <= i;`
194			`for n in 1 to n_stages-1 loop`
195			`reg(n) <= reg(n-1);`
196			`end loop;`
197			`end if;`
198			`end if; -- rising_edge()`
199			`end process;`
200			`o <= reg(n_stages-1);`
201			`end generate;`
202
203			`end rtl;`
204
205
206
207
208			`----------------------------------------------------------------------------------------------------`
209			`-- boolean version`
210			`--`
211			`-- boolean, integer and float are unresolved types.`
212			`-- Modelsim warns for these about potential multisource assignments.`
213			`-- This is harmless. n_stages is still unknown when the architecture is compiled.`
214			`-- Nevertheless the compiler could see that whatever n_stages might be,`
215			`-- it cannot be 1 AND 2 at the same time.`
216
217			`library IEEE;`
218			`use IEEE.STD_LOGIC_1164.ALL;`
219			`use IEEE.numeric_std.all;`
220
221			`entity bool_pipestage is`
222			`generic (`
223			`n_stages: natural := 1`
224			`);`
225			`Port (`
226			`clk: in std_logic;`
227			`ce: in std_logic := '1';`
228			`rst: in std_logic;`
229
230			`i: in boolean;`
231			`o: out boolean`
232			`);`
233			`end bool_pipestage;`
234
235
236
237			`architecture rtl of bool_pipestage is`
238
239			`begin`
240
241			`ns0: if n_stages = 0`
242			`generate`
243			`begin`
244			`o <= i;`
245			`end generate;`
246
247
248			`ns1: if n_stages = 1`
249			`generate`
250			`begin`
251			`u_reg: process(clk)`
252			`begin`
253			`if rising_edge(clk)`
254			`then`
255			`if rst = '1'`
256			`then`
257			`o <= false;`
258			`elsif ce = '1'`
259			`then`
260			`o <= i;`
261			`end if;`
262			`end if; -- rising_edge()`
263			`end process;`
264			`end generate;`
265
266
267			`ns2: if n_stages >= 2`
268			`generate`
269			`type bla is array(0 to n_stages-1) of boolean;`
270			`signal reg: bla;`
271			`begin`
272			`u_reg: process(clk)`
273			`begin`
274			`if rising_edge(clk)`
275			`then`
276			`if rst = '1'`
277			`then`
278			`for n in reg'range loop`
279			`reg(n) <= false;`
280			`end loop;`
281			`elsif ce = '1'`
282			`then`
283			`reg(0) <= i;`
284			`for n in 1 to n_stages-1 loop`
285			`reg(n) <= reg(n-1);`
286			`end loop;`
287			`end if;`
288			`end if; -- rising_edge()`
289			`end process;`
290			`o <= reg(n_stages-1);`
291			`end generate;`
292
293			`end rtl;`
294
295
296
297			`----------------------------------------------------------------------------------------------------`
298			`-- signed version`
299
300			`library IEEE;`
301			`use IEEE.STD_LOGIC_1164.ALL;`
302			`use IEEE.numeric_std.all;`
303
304			`entity signed_pipestage is`
305			`generic (`
306			`n_stages: natural := 1`
307			`);`
308			`Port (`
309			`clk: in std_logic;`
310			`ce: in std_logic := '1';`
311			`rst: in std_logic := '0';`
312
313			`i: in signed;`
314			`o: out signed`
315			`);`
316			`end signed_pipestage;`
317
318
319			`architecture rtl of signed_pipestage is`
320
321
322			`function blow_up(b: std_logic; s: integer) return signed is`
323			`variable r: signed(s-1 downto 0);`
324			`begin`
325			`for n in 0 to s-1 loop`
326			`r(n) := b;`
327			`end loop;`
328			`return r;`
329			`end;`
330
331
332			`begin`
333
334			`assert i'length = o'length`
335			`report "signed_pipestage: input and output length do not match: "`
336			`& integer'image(i'length)`
337			`& " vs. "`
338			`& integer'image(o'length)`
339			`severity error;`
340
341
342			`ns0: if n_stages = 0`
343			`generate`
344			`begin`
345			`o <= i;`
346			`end generate;`
347
348
349			`ns1: if n_stages = 1`
350			`generate`
351			`begin`
352			`u_reg: process(clk)`
353			`begin`
354			`if rising_edge(clk)`
355			`then`
356			`if rst = '1'`
357			`then`
358			`o <= blow_up('0', o'length);`
359			`elsif ce = '1'`
360			`then`
361			`o <= i;`
362			`end if;`
363			`end if; -- rising_edge()`
364			`end process;`
365			`end generate;`
366
367
368
369			`ns2: if n_stages >= 2`
370			`generate`
371			`type bla is array(0 to n_stages-1) of signed(i'range);`
372			`signal reg: bla;`
373			`begin`
374			`u_reg: process(clk)`
375			`begin`
376			`if rising_edge(clk)`
377			`then`
378			`if rst = '1'`
379			`then`
380			`for n in reg'range loop`
381			`reg(n) <= blow_up('0', o'length);`
382			`end loop;`
383			`elsif ce = '1'`
384			`then`
385			`reg(0) <= i;`
386			`for n in 1 to n_stages-1 loop`
387			`reg(n) <= reg(n-1);`
388			`end loop;`
389			`end if;`
390			`end if; -- rising_edge()`
391			`end process;`
392			`o <= reg(n_stages-1);`
393			`end generate;`
394
395			`end rtl;`
396
397			`----------------------------------------------------------------------------------------------------`
398			`-- unsigned version`
399
400			`library IEEE;`
401			`use IEEE.STD_LOGIC_1164.ALL;`
402			`use IEEE.numeric_std.all;`
403
404			`entity unsigned_pipestage is`
405			`generic (`
406			`n_stages: natural := 1 -- 0 to quite a few`
407			`);`
408			`Port (`
409			`clk: in std_logic;`
410			`ce: in std_logic := '1';`
411			`rst: in std_logic := '0';`
412
413			`i: in unsigned;`
414			`o: out unsigned`
415			`);`
416			`end unsigned_pipestage;`
417
418
419
420			`architecture rtl of unsigned_pipestage is`
421
422
423			`function blow_up(b: std_logic; s: integer) return unsigned is`
424			`variable r: unsigned(s-1 downto 0);`
425			`begin`
426			`for n in 0 to s-1 loop`
427			`r(n) := b;`
428			`end loop;`
429			`return r;`
430			`end;`
431
432
433			`begin`
434
435			`assert i'length = o'length`
436			`report "unsigned_pipestage: input and output length do not match: "`
437			`& integer'image(i'length)`
438			`& " vs. "`
439			`& integer'image(o'length)`
440			`severity error;`
441
442
443			`ns0: if n_stages = 0`
444			`generate`
445			`begin`
446			`o <= i;`
447			`end generate;`
448
449
450			`ns1: if n_stages = 1`
451			`generate`
452			`begin`
453			`u_reg: process(clk)`
454			`begin`
455			`if rising_edge(clk)`
456			`then`
457			`if rst = '1'`
458			`then`
459			`o <= blow_up('0', o'length);`
460			`elsif ce = '1'`
461			`then`
462			`o <= i;`
463			`end if;`
464			`end if; -- rising_edge()`
465			`end process;`
466			`end generate;`
467
468
469
470			`ns2: if n_stages >= 2`
471			`generate`
472			`type bla is array(0 to n_stages-1) of unsigned(i'range);`
473			`signal reg: bla;`
474			`begin`
475			`u_reg: process(clk)`
476			`begin`
477			`if rising_edge(clk)`
478			`then`
479			`if rst = '1'`
480			`then`
481			`for n in reg'range loop`
482			`reg(n) <= blow_up('0', o'length);`
483			`end loop;`
484			`elsif ce = '1'`
485			`then`
486			`reg(0) <= i;`
487			`for n in 1 to n_stages-1 loop`
488			`reg(n) <= reg(n-1);`
489			`end loop;`
490			`end if;`
491			`end if; -- rising_edge()`
492			`end process;`
493			`o <= reg(n_stages-1);`
494			`end generate;`
495
496			`end rtl;`
497
498
499			`----------------------------------------------------------------------------------------------------`
500			`-- integer version`
501
502			`library IEEE;`
503			`use IEEE.STD_LOGIC_1164.ALL;`
504			`use IEEE.numeric_std.all;`
505
506			`entity integer_pipestage is`
507			`generic (`
508			`n_stages: natural := 1`
509			`);`
510			`Port (`
511			`clk: in std_logic;`
512			`ce: in std_logic := '1';`
513			`rst: in std_logic := '0';`
514
515			`i: in integer;`
516			`o: out integer`
517			`);`
518			`end integer_pipestage;`
519
520
521			`architecture rtl of integer_pipestage is`
522
523			`begin`
524
525			`ns0: if n_stages = 0`
526			`generate`
527			`begin`
528			`o <= i;`
529			`end generate;`
530
531
532			`ns1: if n_stages = 1`
533			`generate`
534			`begin`
535			`u_reg: process(clk)`
536			`begin`
537			`if rising_edge(clk)`
538			`then`
539			`if rst = '1'`
540			`then`
541			`o <= 0;`
542			`elsif ce = '1'`
543			`then`
544			`o <= i;`
545			`end if;`
546			`end if; -- rising_edge()`
547			`end process;`
548			`end generate;`
549
550
551			`ns2: if n_stages >= 2`
552			`generate`
553			`type bla is array(0 to n_stages-1) of integer;`
554			`signal reg: bla;`
555			`begin`
556			`u_reg: process(clk)`
557			`begin`
558			`if rising_edge(clk)`
559			`then`
560			`if rst = '1'`
561			`then`
562			`for n in reg'range loop`
563			`reg(n) <= 0;`
564			`end loop;`
565			`elsif ce = '1'`
566			`then`
567			`reg(0) <= i;`
568			`for n in 1 to n_stages-1 loop`
569			`reg(n) <= reg(n-1);`
570			`end loop;`
571			`end if;`
572			`end if; -- rising_edge()`
573			`end process;`
574			`o <= reg(n_stages-1);`
575			`end generate;`
576
577			`end rtl;`
578
579
580			`----------------------------------------------------------------------------------------------------`
581			`-- real version`
582
583			`library IEEE;`
584			`use IEEE.STD_LOGIC_1164.ALL;`
585			`use IEEE.numeric_std.all;`
586
587			`entity real_pipestage is`
588			`generic (`
589			`n_stages: natural := 1`
590			`);`
591			`Port (`
592			`clk: in std_logic;`
593			`ce: in std_logic := '1';`
594			`rst: in std_logic := '0';`
595
596			`i: in real;`
597			`o: out real`
598			`);`
599			`end real_pipestage;`
600
601
602
603
604			`architecture rtl of real_pipestage is`
605
606			`begin`
607
608			`ns0: if n_stages = 0`
609			`generate`
610			`begin`
611			`o <= i;`
612			`end generate;`
613
614
615			`ns1: if n_stages = 1`
616			`generate`
617			`begin`
618			`u_reg: process(clk)`
619			`begin`
620			`if rising_edge(clk)`
621			`then`
622			`if rst = '1'`
623			`then`
624			`o <= 0.0;`
625			`elsif ce = '1'`
626			`then`
627			`o <= i;`
628			`end if;`
629			`end if; -- rising_edge()`
630			`end process;`
631			`end generate;`
632
633
634			`ns2: if n_stages >= 2`
635			`generate`
636			`type bla is array(0 to n_stages-1) of real;`
637			`signal reg: bla;`
638			`begin`
639			`u_reg: process(clk)`
640			`begin`
641			`if rising_edge(clk)`
642			`then`
643			`if rst = '1'`
644			`then`
645			`for n in reg'range loop`
646			`reg(n) <= 0.0;`
647			`end loop;`
648			`elsif ce = '1'`
649			`then`
650			`reg(0) <= i;`
651			`for n in 1 to n_stages-1 loop`
652			`reg(n) <= reg(n-1);`
653			`end loop;`
654			`end if;`
655			`end if; -- rising_edge()`
656			`end process;`
657			`o <= reg(n_stages-1);`
658			`end generate;`
659
660			`end rtl;`
661
662
663
664
665			`--------------------------------------------------------------------------------------------------`
666			`-- unsigned fixed point version`
667			`--`
668			`-- If you don't have / cannot compile the floatfixlib, comment out the rest of the file.`
669			`-- David Bishop's version as supplied with Modelsim 6.5 seems to work with ISE 12.3, too.`
670			`--`
671
672			`library IEEE;`
673			`use IEEE.STD_LOGIC_1164.ALL;`
674			`use IEEE.numeric_std.all;`
675			`library floatfixlib;`
676			`use floatfixlib.fixed_pkg.all;`
677
678			`entity ufixed_pipestage is`
679			`generic (`
680			`n_stages: natural := 1`
681			`);`
682			`Port (`
683			`clk: in std_logic;`
684			`ce: in std_logic := '1';`
685			`rst: in std_logic := '0';`
686
687			`i: in ufixed;`
688			`o: out ufixed`
689			`);`
690			`end ufixed_pipestage;`
691
692
693
694			`architecture rtl of ufixed_pipestage is`
695
696
697			`function blow_up(b: std_logic; s: integer) return ufixed is`
698			`variable r: ufixed(s-1 downto 0);`
699			`begin`
700			`for n in 0 to s-1 loop`
701			`r(n) := b;`
702			`end loop;`
703			`return r;`
704			`end;`
705
706
707			`begin`
708
709			`assert i'length = o'length`
710			`report "ufixed_pipestage: input and output length do not match: "`
711			`& integer'image(i'length)`
712			`& " vs. "`
713			`& integer'image(o'length)`
714			`severity error;`
715
716
717			`ns0: if n_stages = 0`
718			`generate`
719			`begin`
720			`o <= i;`
721			`end generate;`
722
723
724			`ns1: if n_stages = 1`
725			`generate`
726			`begin`
727			`u_reg: process(clk)`
728			`begin`
729			`if rising_edge(clk)`
730			`then`
731			`if rst = '1'`
732			`then`
733			`o <= blow_up('0', o'length);`
734			`elsif ce = '1'`
735			`then`
736			`o <= i;`
737			`end if;`
738			`end if; -- rising_edge()`
739			`end process;`
740			`end generate;`
741
742
743
744			`ns2: if n_stages >= 2`
745			`generate`
746			`type bla is array(0 to n_stages-1) of ufixed(i'range);`
747			`signal reg: bla;`
748			`begin`
749			`u_reg: process(clk)`
750			`begin`
751			`if rising_edge(clk)`
752			`then`
753			`if rst = '1'`
754			`then`
755			`for n in reg'range loop`
756			`reg(n) <= blow_up('0', o'length);`
757			`end loop;`
758			`elsif ce = '1'`
759			`then`
760			`reg(0) <= i;`
761			`for n in 1 to n_stages-1 loop`
762			`reg(n) <= reg(n-1);`
763			`end loop;`
764			`end if;`
765			`end if; -- rising_edge()`
766			`end process;`
767			`o <= reg(n_stages-1);`
768			`end generate;`
769
770			`end rtl;`
771
772
773
774			`----------------------------------------------------------------------------------------------------`
775			`-- signed fixed point version`
776			`--`
777			`library IEEE;`
778			`use IEEE.STD_LOGIC_1164.ALL;`
779			`use IEEE.numeric_std.all;`
780			`library floatfixlib;`
781			`use floatfixlib.fixed_pkg.all;`
782
783			`entity sfixed_pipestage is`
784			`generic (`
785			`n_stages: natural := 1`
786			`);`
787			`Port (`
788			`clk: in std_logic;`
789			`ce: in std_logic := '1';`
790			`rst: in std_logic := '0';`
791
792			`i: in sfixed;`
793			`o: out sfixed`
794			`);`
795			`end sfixed_pipestage;`
796
797
798
799			`architecture rtl of sfixed_pipestage is`
800
801
802			`function blow_up(b: std_logic; s: integer) return sfixed is`
803			`variable r: sfixed(s-1 downto 0);`
804			`begin`
805			`for n in 0 to s-1 loop`
806			`r(n) := b;`
807			`end loop;`
808			`return r;`
809			`end;`
810
811
812			`begin`
813
814			`assert i'length = o'length`
815			`report "sfixed_pipestage: input and output length do not match: "`
816			`& integer'image(i'length)`
817			`& " vs. "`
818			`& integer'image(o'length)`
819			`severity error;`
820
821
822			`ns0: if n_stages = 0`
823			`generate`
824			`begin`
825			`o <= i;`
826			`end generate;`
827
828
829			`ns1: if n_stages = 1`
830			`generate`
831			`begin`
832			`u_reg: process(clk)`
833			`begin`
834			`if rising_edge(clk)`
835			`then`
836			`if rst = '1'`
837			`then`
838			`o <= blow_up('0', o'length);`
839			`elsif ce = '1'`
840			`then`
841			`o <= i;`
842			`end if;`
843			`end if; -- rising_edge()`
844			`end process;`
845			`end generate;`
846
847
848
849			`ns2: if n_stages >= 2`
850			`generate`
851			`type bla is array(0 to n_stages-1) of sfixed(i'range);`
852			`signal reg: bla;`
853			`begin`
854			`u_reg: process(clk)`
855			`begin`
856			`if rising_edge(clk)`
857			`then`
858			`if rst = '1'`
859			`then`
860			`for n in reg'range loop`
861			`reg(n) <= blow_up('0', o'length);`
862			`end loop;`
863			`elsif ce = '1'`
864			`then`
865			`reg(0) <= i;`
866			`for n in 1 to n_stages-1 loop`
867			`reg(n) <= reg(n-1);`
868			`end loop;`
869			`end if;`
870			`end if; -- rising_edge()`
871			`end process;`
872			`o <= reg(n_stages-1);`
873			`end generate;`
874
875			`end rtl;`
876