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[/] [sincos/] [trunk/] [vhdl/] [msi/] [pipestage/] [pipestage_tb.vhd] - Blame information for rev 15

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----------------------------------------------------------------------------------------------------
-- (c) 2005.. Hoffmann RF & DSP   opencores@hoffmann-hochfrequenz.de
-- V1.0 published under BSD license
----------------------------------------------------------------------------------------------------
-- Design Name:     pipestage_tb.vhd
-- Tool versions:   Modelsim
-- Description:           testbed for pipeline stage with variable width and depth
 
-- calls lib:       ieee standard
-- calls entities:  clk_rst, several flavours of pipestage.vhd
--
----------------------------------------------------------------------------------------------------
 
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
 
library floatfixlib;
use floatfixlib.fixed_pkg.all;
 
 
entity pipestage_tb is begin end pipestage_tb;
 
 
architecture tb of pipestage_tb is
 
        signal rst, clk, ce: std_logic := '0';
 
  signal slv_src:                                        std_logic_vector(7 downto 0);
  signal signed_src:                                     signed(7 downto 0);
  signal unsigned_src:                                   unsigned(7 downto 0);
  signal bool_src:                                       boolean;
  signal sl_src:                                         std_logic;
  signal ufixed_src:                                     ufixed(4 downto -3);
  signal sfixed_src:                                     sfixed(4 downto -3);
 
        signal slv_0, slv_1, slv_2, slv_3:                     std_logic_vector(7 downto 0);
        signal signed_0, signed_1, signed_2, signed_3:         signed(7 downto 0);
        signal unsigned_0, unsigned_1, unsigned_2, unsigned_3: unsigned(7 downto 0);
  signal bool_0, bool_1, bool_2, bool_3:                 boolean;
        signal sl_0, sl_1, sl_2, sl_3:                         std_logic;
        signal ufixed_0, ufixed_1, ufixed_2, ufixed_3:         ufixed(3 downto -4);   -- warum zeigt der Modelsim Indizes von 4 bis -3 ?????
        signal sfixed_0, sfixed_1, sfixed_2, sfixed_3:         sfixed(3 downto -4);
 
-- floats and integers receive enough testing in the sine table module.
 
begin
 
u_clk_rst: entity work.clk_rst
generic  map(
  verbose           => false,
  clock_frequency   => 100.0e6,
  min_resetwidth    => 15 ns
)
port map(
  clk               => clk,
  rst               => rst
);
 
 
--p_mk_ce: process(clk) is begin
--      if rising_edge(clk) then
--              if rst='1' then
--                      ce <= '1';
--               else
--                      ce <= not ce;
--              end if;
--      end if;
--end process;
 
ce <= '1';
 
p_stimulus: process(clk) is begin
        if rising_edge(clk) then
                if rst='1' then
                        slv_src <= x"00";
      bool_src <= false;
                 else
                        slv_src <= std_logic_vector(unsigned(slv_src) + 1);
      bool_src <= (slv_src(0)='0') and (slv_src(1)='0') and (slv_src(2)='0');
                end if;
        end if;
end process;
 
sl_src       <= slv_src(3);
signed_src   <= signed(slv_src);
unsigned_src <= unsigned(slv_src);
 
ufixed_src   <= to_ufixed(0,     ufixed_src),
                to_ufixed(3.0,   ufixed_src) after 92 ns,
                to_ufixed(3.75,  ufixed_src) after 152 ns;
 
sfixed_src   <= to_sfixed(0,     sfixed_src),
                to_sfixed(3.0,   sfixed_src) after 92 ns,
                to_sfixed(-3.75, sfixed_src) after 152 ns;
 
--------------------------------------------------------------------------------
-- std_logic_vector version
 
u_slv_0:        entity work.slv_pipestage
generic map (
  n_stages      => 0
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => slv_src,
        o   => slv_0
);
 
 
u_slv_1:        entity work.slv_pipestage
generic map (
  n_stages      => 1
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => slv_src,
  o   => slv_1
);
 
 
u_slv_2:        entity work.slv_pipestage
generic map (
  n_stages      => 2
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => slv_src,
  o   => slv_2
);
 
 
u_slv_3:        entity work.slv_pipestage
generic map (
  n_stages      => 3
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => slv_src,
  o   => slv_3
);
 
 
--------------------------------------------------------------------------------
-- boolean version
 
 
u_bool_0:       entity work.bool_pipestage
generic map (
  n_stages      => 0
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => bool_src,
        o   => bool_0
);
 
 
u_bool_1:       entity work.bool_pipestage
generic map (
  n_stages      => 1
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => bool_src,
  o   => bool_1
);
 
 
u_bool_2:       entity work.bool_pipestage
generic map (
  n_stages      => 2
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => bool_src,
  o   => bool_2
);
 
 
u_bool_3:       entity work.bool_pipestage
generic map (
  n_stages      => 3
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => bool_src,
  o   => bool_3
);
 
 
--------------------------------------------------------------------------------
-- std_logic version
 
u_sl_0: entity work.sl_pipestage
generic map (
  n_stages      => 0
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => sl_src,
        o   => sl_0
);
 
 
u_sl_1: entity work.sl_pipestage
generic map (
  n_stages      => 1
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => sl_src,
  o   => sl_1
);
 
 
u_sl_2: entity work.sl_pipestage
generic map (
  n_stages      => 2
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => sl_src,
  o   => sl_2
);
 
 
u_sl_3: entity work.sl_pipestage
generic map (
  n_stages      => 3
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => sl_src,
  o   => sl_3
);
 
 
--------------------------------------------------------------------------------
-- signed version
 
u_signed_0:     entity work.signed_pipestage
generic map (
  n_stages      => 0
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => signed_src,
  o   => signed_0
);
 
 
u_signed_1:     entity work.signed_pipestage
generic map (
  n_stages      => 1
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => signed_src,
  o   => signed_1
);
 
 
u_signed_2:     entity work.signed_pipestage
generic map (
  n_stages      => 2
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => signed_src,
  o   => signed_2
);
 
 
u_signed_3:     entity work.signed_pipestage
generic map (
  n_stages      => 3
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => signed_src,
  o   => signed_3
);
 
 
--------------------------------------------------------------------------------
-- unsigned version
 
u_unsigned_0:   entity work.unsigned_pipestage
generic map (
  n_stages      => 0
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => unsigned_src,
        o   => unsigned_0
);
 
 
u_unsigned_1:   entity work.unsigned_pipestage
generic map (
  n_stages      => 1
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => unsigned_src,
  o   => unsigned_1
);
 
 
u_unsigned_2:   entity work.unsigned_pipestage
generic map (
  n_stages      => 2
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => unsigned_src,
  o   => unsigned_2
);
 
 
u_unsigned_3:   entity work.unsigned_pipestage
generic map (
  n_stages      => 3
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => unsigned_src,
  o   => unsigned_3
);
 
-- real and integer still missing  FIXME
 
 
--------------------------------------------------------------------------------
-- ufixed version
 
u_ufix_0:       entity work.ufixed_pipestage
generic map (
  n_stages      => 0
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => ufixed_src,
        o   => ufixed_0
);
 
 
u_ufix_1:       entity work.ufixed_pipestage
generic map (
  n_stages      => 1
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => ufixed_src,
  o   => ufixed_1
);
 
 
u_ufix_2:       entity work.ufixed_pipestage
generic map (
  n_stages      => 2
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => ufixed_src,
  o   => ufixed_2
);
 
 
u_ufix_3:       entity work.ufixed_pipestage
generic map (
  n_stages      => 3
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => ufixed_src,
  o   => ufixed_3
);
 
 
 
--------------------------------------------------------------------------------
-- sfixed version
 
u_sfix_0:       entity work.sfixed_pipestage
generic map (
  n_stages      => 0
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => sfixed_src,
        o   => sfixed_0
);
 
 
u_sfix_1:       entity work.sfixed_pipestage
generic map (
  n_stages      => 1
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => sfixed_src,
  o   => sfixed_1
);
 
 
u_sfix_2:       entity work.sfixed_pipestage
generic map (
  n_stages      => 2
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => sfixed_src,
  o   => sfixed_2
);
 
 
u_sfix_3:       entity work.sfixed_pipestage
generic map (
  n_stages      => 3
)
Port map (
  clk => clk,
  ce  => ce,
  rst => rst,
 
  i   => sfixed_src,
  o   => sfixed_3
);
 
 
end tb;
 
 

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[/] [sincos/] [trunk/] [vhdl/] [msi/] [pipestage/] [pipestage_tb.vhd] - Blame information for rev 15

Line No.	Rev	Author	Line
1	15	dk4xp	`----------------------------------------------------------------------------------------------------`
2			`-- (c) 2005.. Hoffmann RF & DSP opencores@hoffmann-hochfrequenz.de`
3			`-- V1.0 published under BSD license`
4			`----------------------------------------------------------------------------------------------------`
5			`-- Design Name: pipestage_tb.vhd`
6			`-- Tool versions: Modelsim`
7			`-- Description: testbed for pipeline stage with variable width and depth`
8
9			`-- calls lib: ieee standard`
10			`-- calls entities: clk_rst, several flavours of pipestage.vhd`
11			`--`
12			`----------------------------------------------------------------------------------------------------`
13
14			`library IEEE;`
15			`use IEEE.STD_LOGIC_1164.ALL;`
16			`use IEEE.numeric_std.all;`
17
18			`library floatfixlib;`
19			`use floatfixlib.fixed_pkg.all;`
20
21
22			`entity pipestage_tb is begin end pipestage_tb;`
23
24
25			`architecture tb of pipestage_tb is`
26
27			`signal rst, clk, ce: std_logic := '0';`
28
29			`signal slv_src: std_logic_vector(7 downto 0);`
30			`signal signed_src: signed(7 downto 0);`
31			`signal unsigned_src: unsigned(7 downto 0);`
32			`signal bool_src: boolean;`
33			`signal sl_src: std_logic;`
34			`signal ufixed_src: ufixed(4 downto -3);`
35			`signal sfixed_src: sfixed(4 downto -3);`
36
37			`signal slv_0, slv_1, slv_2, slv_3: std_logic_vector(7 downto 0);`
38			`signal signed_0, signed_1, signed_2, signed_3: signed(7 downto 0);`
39			`signal unsigned_0, unsigned_1, unsigned_2, unsigned_3: unsigned(7 downto 0);`
40			`signal bool_0, bool_1, bool_2, bool_3: boolean;`
41			`signal sl_0, sl_1, sl_2, sl_3: std_logic;`
42			`signal ufixed_0, ufixed_1, ufixed_2, ufixed_3: ufixed(3 downto -4); -- warum zeigt der Modelsim Indizes von 4 bis -3 ?????`
43			`signal sfixed_0, sfixed_1, sfixed_2, sfixed_3: sfixed(3 downto -4);`
44
45			`-- floats and integers receive enough testing in the sine table module.`
46
47			`begin`
48
49			`u_clk_rst: entity work.clk_rst`
50			`generic map(`
51			`verbose => false,`
52			`clock_frequency => 100.0e6,`
53			`min_resetwidth => 15 ns`
54			`)`
55			`port map(`
56			`clk => clk,`
57			`rst => rst`
58			`);`
59
60
61			`--p_mk_ce: process(clk) is begin`
62			`-- if rising_edge(clk) then`
63			`-- if rst='1' then`
64			`-- ce <= '1';`
65			`-- else`
66			`-- ce <= not ce;`
67			`-- end if;`
68			`-- end if;`
69			`--end process;`
70
71			`ce <= '1';`
72
73			`p_stimulus: process(clk) is begin`
74			`if rising_edge(clk) then`
75			`if rst='1' then`
76			`slv_src <= x"00";`
77			`bool_src <= false;`
78			`else`
79			`slv_src <= std_logic_vector(unsigned(slv_src) + 1);`
80			`bool_src <= (slv_src(0)='0') and (slv_src(1)='0') and (slv_src(2)='0');`
81			`end if;`
82			`end if;`
83			`end process;`
84
85			`sl_src <= slv_src(3);`
86			`signed_src <= signed(slv_src);`
87			`unsigned_src <= unsigned(slv_src);`
88
89			`ufixed_src <= to_ufixed(0, ufixed_src),`
90			`to_ufixed(3.0, ufixed_src) after 92 ns,`
91			`to_ufixed(3.75, ufixed_src) after 152 ns;`
92
93			`sfixed_src <= to_sfixed(0, sfixed_src),`
94			`to_sfixed(3.0, sfixed_src) after 92 ns,`
95			`to_sfixed(-3.75, sfixed_src) after 152 ns;`
96
97			`--------------------------------------------------------------------------------`
98			`-- std_logic_vector version`
99
100			`u_slv_0: entity work.slv_pipestage`
101			`generic map (`
102			`n_stages => 0`
103			`)`
104			`Port map (`
105			`clk => clk,`
106			`ce => ce,`
107			`rst => rst,`
108
109			`i => slv_src,`
110			`o => slv_0`
111			`);`
112
113
114			`u_slv_1: entity work.slv_pipestage`
115			`generic map (`
116			`n_stages => 1`
117			`)`
118			`Port map (`
119			`clk => clk,`
120			`ce => ce,`
121			`rst => rst,`
122
123			`i => slv_src,`
124			`o => slv_1`
125			`);`
126
127
128			`u_slv_2: entity work.slv_pipestage`
129			`generic map (`
130			`n_stages => 2`
131			`)`
132			`Port map (`
133			`clk => clk,`
134			`ce => ce,`
135			`rst => rst,`
136
137			`i => slv_src,`
138			`o => slv_2`
139			`);`
140
141
142			`u_slv_3: entity work.slv_pipestage`
143			`generic map (`
144			`n_stages => 3`
145			`)`
146			`Port map (`
147			`clk => clk,`
148			`ce => ce,`
149			`rst => rst,`
150
151			`i => slv_src,`
152			`o => slv_3`
153			`);`
154
155
156			`--------------------------------------------------------------------------------`
157			`-- boolean version`
158
159
160			`u_bool_0: entity work.bool_pipestage`
161			`generic map (`
162			`n_stages => 0`
163			`)`
164			`Port map (`
165			`clk => clk,`
166			`ce => ce,`
167			`rst => rst,`
168
169			`i => bool_src,`
170			`o => bool_0`
171			`);`
172
173
174			`u_bool_1: entity work.bool_pipestage`
175			`generic map (`
176			`n_stages => 1`
177			`)`
178			`Port map (`
179			`clk => clk,`
180			`ce => ce,`
181			`rst => rst,`
182
183			`i => bool_src,`
184			`o => bool_1`
185			`);`
186
187
188			`u_bool_2: entity work.bool_pipestage`
189			`generic map (`
190			`n_stages => 2`
191			`)`
192			`Port map (`
193			`clk => clk,`
194			`ce => ce,`
195			`rst => rst,`
196
197			`i => bool_src,`
198			`o => bool_2`
199			`);`
200
201
202			`u_bool_3: entity work.bool_pipestage`
203			`generic map (`
204			`n_stages => 3`
205			`)`
206			`Port map (`
207			`clk => clk,`
208			`ce => ce,`
209			`rst => rst,`
210
211			`i => bool_src,`
212			`o => bool_3`
213			`);`
214
215
216			`--------------------------------------------------------------------------------`
217			`-- std_logic version`
218
219			`u_sl_0: entity work.sl_pipestage`
220			`generic map (`
221			`n_stages => 0`
222			`)`
223			`Port map (`
224			`clk => clk,`
225			`ce => ce,`
226			`rst => rst,`
227
228			`i => sl_src,`
229			`o => sl_0`
230			`);`
231
232
233			`u_sl_1: entity work.sl_pipestage`
234			`generic map (`
235			`n_stages => 1`
236			`)`
237			`Port map (`
238			`clk => clk,`
239			`ce => ce,`
240			`rst => rst,`
241
242			`i => sl_src,`
243			`o => sl_1`
244			`);`
245
246
247			`u_sl_2: entity work.sl_pipestage`
248			`generic map (`
249			`n_stages => 2`
250			`)`
251			`Port map (`
252			`clk => clk,`
253			`ce => ce,`
254			`rst => rst,`
255
256			`i => sl_src,`
257			`o => sl_2`
258			`);`
259
260
261			`u_sl_3: entity work.sl_pipestage`
262			`generic map (`
263			`n_stages => 3`
264			`)`
265			`Port map (`
266			`clk => clk,`
267			`ce => ce,`
268			`rst => rst,`
269
270			`i => sl_src,`
271			`o => sl_3`
272			`);`
273
274
275			`--------------------------------------------------------------------------------`
276			`-- signed version`
277
278			`u_signed_0: entity work.signed_pipestage`
279			`generic map (`
280			`n_stages => 0`
281			`)`
282			`Port map (`
283			`clk => clk,`
284			`ce => ce,`
285			`rst => rst,`
286
287			`i => signed_src,`
288			`o => signed_0`
289			`);`
290
291
292			`u_signed_1: entity work.signed_pipestage`
293			`generic map (`
294			`n_stages => 1`
295			`)`
296			`Port map (`
297			`clk => clk,`
298			`ce => ce,`
299			`rst => rst,`
300
301			`i => signed_src,`
302			`o => signed_1`
303			`);`
304
305
306			`u_signed_2: entity work.signed_pipestage`
307			`generic map (`
308			`n_stages => 2`
309			`)`
310			`Port map (`
311			`clk => clk,`
312			`ce => ce,`
313			`rst => rst,`
314
315			`i => signed_src,`
316			`o => signed_2`
317			`);`
318
319
320			`u_signed_3: entity work.signed_pipestage`
321			`generic map (`
322			`n_stages => 3`
323			`)`
324			`Port map (`
325			`clk => clk,`
326			`ce => ce,`
327			`rst => rst,`
328
329			`i => signed_src,`
330			`o => signed_3`
331			`);`
332
333
334			`--------------------------------------------------------------------------------`
335			`-- unsigned version`
336
337			`u_unsigned_0: entity work.unsigned_pipestage`
338			`generic map (`
339			`n_stages => 0`
340			`)`
341			`Port map (`
342			`clk => clk,`
343			`ce => ce,`
344			`rst => rst,`
345
346			`i => unsigned_src,`
347			`o => unsigned_0`
348			`);`
349
350
351			`u_unsigned_1: entity work.unsigned_pipestage`
352			`generic map (`
353			`n_stages => 1`
354			`)`
355			`Port map (`
356			`clk => clk,`
357			`ce => ce,`
358			`rst => rst,`
359
360			`i => unsigned_src,`
361			`o => unsigned_1`
362			`);`
363
364
365			`u_unsigned_2: entity work.unsigned_pipestage`
366			`generic map (`
367			`n_stages => 2`
368			`)`
369			`Port map (`
370			`clk => clk,`
371			`ce => ce,`
372			`rst => rst,`
373
374			`i => unsigned_src,`
375			`o => unsigned_2`
376			`);`
377
378
379			`u_unsigned_3: entity work.unsigned_pipestage`
380			`generic map (`
381			`n_stages => 3`
382			`)`
383			`Port map (`
384			`clk => clk,`
385			`ce => ce,`
386			`rst => rst,`
387
388			`i => unsigned_src,`
389			`o => unsigned_3`
390			`);`
391
392			`-- real and integer still missing FIXME`
393
394
395			`--------------------------------------------------------------------------------`
396			`-- ufixed version`
397
398			`u_ufix_0: entity work.ufixed_pipestage`
399			`generic map (`
400			`n_stages => 0`
401			`)`
402			`Port map (`
403			`clk => clk,`
404			`ce => ce,`
405			`rst => rst,`
406
407			`i => ufixed_src,`
408			`o => ufixed_0`
409			`);`
410
411
412			`u_ufix_1: entity work.ufixed_pipestage`
413			`generic map (`
414			`n_stages => 1`
415			`)`
416			`Port map (`
417			`clk => clk,`
418			`ce => ce,`
419			`rst => rst,`
420
421			`i => ufixed_src,`
422			`o => ufixed_1`
423			`);`
424
425
426			`u_ufix_2: entity work.ufixed_pipestage`
427			`generic map (`
428			`n_stages => 2`
429			`)`
430			`Port map (`
431			`clk => clk,`
432			`ce => ce,`
433			`rst => rst,`
434
435			`i => ufixed_src,`
436			`o => ufixed_2`
437			`);`
438
439
440			`u_ufix_3: entity work.ufixed_pipestage`
441			`generic map (`
442			`n_stages => 3`
443			`)`
444			`Port map (`
445			`clk => clk,`
446			`ce => ce,`
447			`rst => rst,`
448
449			`i => ufixed_src,`
450			`o => ufixed_3`
451			`);`
452
453
454
455			`--------------------------------------------------------------------------------`
456			`-- sfixed version`
457
458			`u_sfix_0: entity work.sfixed_pipestage`
459			`generic map (`
460			`n_stages => 0`
461			`)`
462			`Port map (`
463			`clk => clk,`
464			`ce => ce,`
465			`rst => rst,`
466
467			`i => sfixed_src,`
468			`o => sfixed_0`
469			`);`
470
471
472			`u_sfix_1: entity work.sfixed_pipestage`
473			`generic map (`
474			`n_stages => 1`
475			`)`
476			`Port map (`
477			`clk => clk,`
478			`ce => ce,`
479			`rst => rst,`
480
481			`i => sfixed_src,`
482			`o => sfixed_1`
483			`);`
484
485
486			`u_sfix_2: entity work.sfixed_pipestage`
487			`generic map (`
488			`n_stages => 2`
489			`)`
490			`Port map (`
491			`clk => clk,`
492			`ce => ce,`
493			`rst => rst,`
494
495			`i => sfixed_src,`
496			`o => sfixed_2`
497			`);`
498
499
500			`u_sfix_3: entity work.sfixed_pipestage`
501			`generic map (`
502			`n_stages => 3`
503			`)`
504			`Port map (`
505			`clk => clk,`
506			`ce => ce,`
507			`rst => rst,`
508
509			`i => sfixed_src,`
510			`o => sfixed_3`
511			`);`
512
513
514			`end tb;`
515
516