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\hypertarget{classtb_1_1test}{}\section{test Architecture Reference}
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\label{classtb_1_1test}\index{test@{test}}
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\subsection*{Processes}
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\begin{DoxyCompactItemize}
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\item
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\mbox{\Hypertarget{classtb_1_1test_aed1460bea841625ed713788c30ae3e33}\label{classtb_1_1test_aed1460bea841625ed713788c30ae3e33}}
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\hyperlink{classtb_1_1test_aed1460bea841625ed713788c30ae3e33}{P\+R\+O\+C\+E\+S\+S\+\_\+0}{\bfseries ( )}
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\end{DoxyCompactItemize}
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\subsection*{Components}
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\begin{DoxyCompactItemize}
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\item
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\mbox{\Hypertarget{classtb_1_1test_ad79dbc6f0558f8114eac96731755b419}\label{classtb_1_1test_ad79dbc6f0558f8114eac96731755b419}}
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\hyperlink{classtb_1_1test_ad79dbc6f0558f8114eac96731755b419}{Dist\+Rom\+Ascii\+Decoder} {\bfseries }
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\end{DoxyCompactItemize}
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\subsection*{Signals}
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\begin{DoxyCompactItemize}
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\item
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\mbox{\Hypertarget{classtb_1_1test_a0a0ab64c112c667e107064548bef27b0}\label{classtb_1_1test_a0a0ab64c112c667e107064548bef27b0}}
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\hyperlink{classtb_1_1test_a0a0ab64c112c667e107064548bef27b0}{Address} {\bfseries \textcolor{comment}{std\+\_\+logic\+\_\+vector}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{(}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{ } \textcolor{vhdldigit}{6} \textcolor{vhdlchar}{ }\textcolor{keywordflow}{downto}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{ } \textcolor{vhdldigit}{0} \textcolor{vhdlchar}{ }\textcolor{vhdlchar}{)}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{\+:}\textcolor{vhdlchar}{=}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{(}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{ }\textcolor{keywordflow}{others}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{=}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{$>$}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{\textquotesingle{}}\textcolor{vhdlchar}{ } \textcolor{vhdldigit}{0} \textcolor{vhdlchar}{ }\textcolor{vhdlchar}{\textquotesingle{}}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{)}\textcolor{vhdlchar}{ }}
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\item
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\mbox{\Hypertarget{classtb_1_1test_ac142ba3fd33d41ec006fb41f6b872e2f}\label{classtb_1_1test_ac142ba3fd33d41ec006fb41f6b872e2f}}
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\hyperlink{classtb_1_1test_ac142ba3fd33d41ec006fb41f6b872e2f}{Q} {\bfseries \textcolor{comment}{std\+\_\+logic\+\_\+vector}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{(}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{ } \textcolor{vhdldigit}{13} \textcolor{vhdlchar}{ }\textcolor{keywordflow}{downto}\textcolor{vhdlchar}{ }\textcolor{vhdlchar}{ } \textcolor{vhdldigit}{0} \textcolor{vhdlchar}{ }\textcolor{vhdlchar}{)}\textcolor{vhdlchar}{ }}
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\end{DoxyCompactItemize}
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\subsection*{Instantiations}
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\begin{DoxyCompactItemize}
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\item
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\mbox{\Hypertarget{classtb_1_1test_a8026a39c502750413402a90d9d8bae3c}\label{classtb_1_1test_a8026a39c502750413402a90d9d8bae3c}}
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\hyperlink{classtb_1_1test_a8026a39c502750413402a90d9d8bae3c}{u1} {\bfseries Dist\+Rom\+Ascii\+Decoder}
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\end{DoxyCompactItemize}
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The documentation for this class was generated from the following file\+:\begin{DoxyCompactItemize}
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\item
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C\+:/\+Projects/single-\/14-\/segment-\/display-\/driver-\/w-\/decoder/\+Project/\+Sources/\+Decoding\+\_\+\+Table/\+R\+O\+M\+\_\+\+A\+S\+C\+I\+I\+\_\+\+Decoder/\+Dist\+Rom\+Ascii\+Decoder/\+Dist\+Rom\+Ascii\+Decoder/tb\+\_\+\+Dist\+Rom\+Ascii\+Decoder\+\_\+tmpl.\+vhd\end{DoxyCompactItemize}
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