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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [.spreadsheet_view.ini] - Blame information for rev 5

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Line No. Rev Author Line
1 5 liubenoff
[General]
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pin_sort_type=0
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pin_sort_ascending=true
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sig_sort_type=0
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sig_sort_ascending=true
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active_Sheet=Port Assignments
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[Port%20Assignments]
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Name="223,0"
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Group%20By="94,1"
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Pin="97,2"
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BANK="72,3"
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BANK_VCC="100,4"
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VREF="70,5"
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IO_TYPE="223,6"
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PULLMODE="137,7"
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DRIVE="77,8"
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SLEWRATE="139,9"
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CLAMP="83,10"
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OPENDRAIN="107,11"
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DIFFRESISTOR="124,12"
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DIFFDRIVE="102,13"
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HYSTERESIS="111,14"
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TERMINATION="121,15"
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Outload%20%28pF%29="113,16"
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MaxSkew="97,17"
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Clock%20Load%20Only="131,18"
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SwitchingID="110,19"
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Ground%20plane%20PCB%20noise%20%28mV%29="206,20"
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Power%20plane%20PCB%20noise%20%28mV%29="200,21"
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SSO%20Allowance%28%25%29="148,22"
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sort_columns="Name,Ascending"
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[Pin%20Assignments]
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Pin="105,0"
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Pad%20Name="111,1"
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Dual%20Function="286,2"
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Polarity="87,3"
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BANK="0,4"
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BANK_VCC="100,5"
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IO_TYPE="223,6"
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Signal%20Name="241,7"
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Signal%20Type="157,8"
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sort_columns="Pin,Ascending"
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[Clock%20Resource]
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Clock%20Type="100,ELLIPSIS"
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Clock%20Name="100,ELLIPSIS"
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Selection="100,ELLIPSIS"
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Quadrant="100,ELLIPSIS"
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[Global%20Preferences]
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Preference%20Name="303,ELLIPSIS"
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Preference%20Value="332,ELLIPSIS"
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[Cell%20Mapping]
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Type="100,ELLIPSIS"
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Name="100,ELLIPSIS"
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Din\Dout="100,ELLIPSIS"
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PIO%20Register="100,ELLIPSIS"
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[Route%20Priority]
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Type="100,ELLIPSIS"
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Name="100,ELLIPSIS"
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Prioritize="100,ELLIPSIS"
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[Timing%20Preferences]
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Preference%20Name="188,ELLIPSIS"
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Preference%20Value="157,ELLIPSIS"
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Preference%20Unit="147,ELLIPSIS"
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[Group]
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Group%20Type\Name="189,ELLIPSIS"
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Value="59,ELLIPSIS"
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[Misc%20Preferences]
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Preference%20Name="172,ELLIPSIS"
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Preference%20Value="157,ELLIPSIS"

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