URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverWrapper_lse.twr] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	liubenoff	`--------------------------------------------------------------------------------`
2			`Lattice Synthesis Timing Report, Version`
3			`Sun Jan 08 00:20:00 2017`
4
5			`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
6			`Copyright (c) 1995 AT&T Corp. All rights reserved.`
7			`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
8			`Copyright (c) 2001 Agere Systems All rights reserved.`
9			`Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.`
10
11			`Report Information`
12			`------------------`
13			`Design: DisplayDriverWrapper`
14			`Constraint file:`
15			`Report level: verbose report, limited to 3 items per constraint`
16			`--------------------------------------------------------------------------------`
17
18
19			`Timing Report Summary`
20			`--------------`
21			`--------------------------------------------------------------------------------`
22			`Constraint \| Constraint\| Actual\|Levels`
23			`--------------------------------------------------------------------------------`
24			`\| \| \|`
25			`--------------------------------------------------------------------------------`
26
27
28			`All constraints were met.`
29
30
31
32			`Timing summary:`
33			`---------------`
34
35			`Timing errors: 0 Score: 0`
36
37			`Constraints cover 0 paths, 0 nets, and 0 connections (0.0% coverage)`
38
39
40			`Peak memory: 104431616 bytes, TRCE: 49152 bytes, DLYMAN: 0 bytes`
41			`CPU_TIME_REPORT: 0 secs`