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<HEAD><TITLE>Lattice Synthesis Timing Report</TITLE>
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<PRE><A name="Map_Twr"></A><B><U><big>Lattice Synthesis Timing Report</big></U></B>
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--------------------------------------------------------------------------------
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Lattice Synthesis Timing Report, Version
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Sun Jan 08 00:20:00 2017
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Design: DisplayDriverWrapper
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Constraint file:
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Report level: verbose report, limited to 3 items per constraint
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--------------------------------------------------------------------------------
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<A name="mtw1_rs"></A><B><U><big>Timing Report Summary</big></U></B>
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--------------
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--------------------------------------------------------------------------------
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Constraint | Constraint| Actual|Levels
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--------------------------------------------------------------------------------
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--------------------------------------------------------------------------------
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All constraints were met.
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<A name="mtw1_ts"></A><B><U><big>Timing summary:</big></U></B>
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---------------
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Timing errors: 0 Score: 0
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Constraints cover 0 paths, 0 nets, and 0 connections (0.0% coverage)
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Peak memory: 104431616 bytes, TRCE: 49152 bytes, DLYMAN: 0 bytes
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CPU_TIME_REPORT: 0 secs
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