URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.dir/] [5_1.par] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log


 
Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
Fri Jan 13 00:54:53 2017
 
PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
Preference file: DisplayDriverwDecoder_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
 
Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.
Design name: DisplayDriverWrapper
NCD version: 3.3
Vendor:      LATTICE
Device:      LFE5UM5G-45F
Package:     CABGA381
Performance: 8
Loading device for application par from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status:                     Final          Version 1.36.
Performance Hardware Data Status:   Final          Version 50.1.
License checked out.
 
 
Ignore Preference Error(s):  True
Device utilization summary:
 
   PIO (prelim)      16/245           6% used
                     16/203           7% bonded
 
   SLICE              0/21924         0% used
 
 
 
Number of Signals: 0
Number of Connections: 0
 
Pin Constraint Summary:
   16 out of 16 pins locked (100% locked).
 
 
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
 
Finished Placer Phase 0.  REAL time: 5 secs
 
Starting Placer Phase 1.
 
Placer score = 0.
Finished Placer Phase 1.  REAL time: 5 secs
 
Starting Placer Phase 2.
.
Placer score =  0
Finished Placer Phase 2.  REAL time: 5 secs
 
 
------------------ Clock Report ------------------
 
Global Clock Resources:
  CLK_PIN    : 0 out of 12 (0%)
  GR_PCLK    : 0 out of 12 (0%)
  PLL        : 0 out of 4 (0%)
  DCS        : 0 out of 2 (0%)
  DCC        : 0 out of 60 (0%)
  CLKDIV     : 0 out of 4 (0%)
 
Quadrant TL Clocks:
 
  PRIMARY  : 0 out of 16 (0%)
 
Quadrant TR Clocks:
 
  PRIMARY  : 0 out of 16 (0%)
 
Quadrant BL Clocks:
 
  PRIMARY  : 0 out of 16 (0%)
 
Quadrant BR Clocks:
 
  PRIMARY  : 0 out of 16 (0%)
 
Edge Clocks:
 
  No edge clock selected.
 
 
--------------- End of Clock Report ---------------
 
 
+
I/O Usage Summary (final):
   16 out of 245 (6.5%) PIO sites used.
   16 out of 203 (7.9%) bonded PIO sites used.
   Number of PIO comps: 16; differential: 0.
   Number of Vref pins used: 0.
 
I/O Bank Usage Summary:
+----------+----------------+------------+------------+------------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+----------------+------------+------------+------------+
| 0        | 0 / 27 (  0%)  | -          | -          | -          |
| 1        | 0 / 33 (  0%)  | -          | -          | -          |
| 2        | 0 / 32 (  0%)  | -          | -          | -          |
| 3        | 14 / 33 ( 42%) | 2.5V       | -          | -          |
| 6        | 1 / 33 (  3%)  | 2.5V       | -          | -          |
| 7        | 0 / 32 (  0%)  | -          | -          | -          |
| 8        | 1 / 13 (  7%)  | 2.5V       | -          | -          |
+----------+----------------+------------+------------+------------+
 
Total placer CPU time: 3 secs
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
INFO - par: The routing stage will be skipped since the design contains no signals and/or connections.
Timing score: 0
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
 
All signals are completely routed.
 
 
PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack> = 
PAR_SUMMARY::Timing score> = 
PAR_SUMMARY::Worst  slack> = 
PAR_SUMMARY::Timing score> = 
PAR_SUMMARY::Number of errors = 0
 
Total CPU  time to completion: 4 secs
Total REAL time to completion: 6 secs
 
par done!
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.

Line No.	Rev	Author	Line
1	5	liubenoff
2			`Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"`
3			`Fri Jan 13 00:54:53 2017`
4
5			`PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.`
6			`Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf`
7			`Preference file: DisplayDriverwDecoder_impl1.prf.`
8			`Placement level-cost: 5-1.`
9			`Routing Iterations: 6`
10
11			`Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.`
12			`Design name: DisplayDriverWrapper`
13			`NCD version: 3.3`
14			`Vendor: LATTICE`
15			`Device: LFE5UM5G-45F`
16			`Package: CABGA381`
17			`Performance: 8`
18			`Loading device for application par from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.`
19			`Package Status: Final Version 1.36.`
20			`Performance Hardware Data Status: Final Version 50.1.`
21			`License checked out.`
22
23
24			`Ignore Preference Error(s): True`
25			`Device utilization summary:`
26
27			`PIO (prelim) 16/245 6% used`
28			`16/203 7% bonded`
29
30			`SLICE 0/21924 0% used`
31
32
33
34			`Number of Signals: 0`
35			`Number of Connections: 0`
36
37			`Pin Constraint Summary:`
38			`16 out of 16 pins locked (100% locked).`
39
40
41			`No signal is selected as Global Set/Reset.`
42			`Starting Placer Phase 0.`
43
44			`Finished Placer Phase 0. REAL time: 5 secs`
45
46			`Starting Placer Phase 1.`
47
48			`Placer score = 0.`
49			`Finished Placer Phase 1. REAL time: 5 secs`
50
51			`Starting Placer Phase 2.`
52			`.`
53			`Placer score = 0`
54			`Finished Placer Phase 2. REAL time: 5 secs`
55
56
57			`------------------ Clock Report ------------------`
58
59			`Global Clock Resources:`
60			`CLK_PIN : 0 out of 12 (0%)`
61			`GR_PCLK : 0 out of 12 (0%)`
62			`PLL : 0 out of 4 (0%)`
63			`DCS : 0 out of 2 (0%)`
64			`DCC : 0 out of 60 (0%)`
65			`CLKDIV : 0 out of 4 (0%)`
66
67			`Quadrant TL Clocks:`
68
69			`PRIMARY : 0 out of 16 (0%)`
70
71			`Quadrant TR Clocks:`
72
73			`PRIMARY : 0 out of 16 (0%)`
74
75			`Quadrant BL Clocks:`
76
77			`PRIMARY : 0 out of 16 (0%)`
78
79			`Quadrant BR Clocks:`
80
81			`PRIMARY : 0 out of 16 (0%)`
82
83			`Edge Clocks:`
84
85			`No edge clock selected.`
86
87
88			`--------------- End of Clock Report ---------------`
89
90
91			`+`
92			`I/O Usage Summary (final):`
93			`16 out of 245 (6.5%) PIO sites used.`
94			`16 out of 203 (7.9%) bonded PIO sites used.`
95			`Number of PIO comps: 16; differential: 0.`
96			`Number of Vref pins used: 0.`
97
98			`I/O Bank Usage Summary:`
99			`+----------+----------------+------------+------------+------------+`
100			`\| I/O Bank \| Usage \| Bank Vccio \| Bank Vref1 \| Bank Vref2 \|`
101			`+----------+----------------+------------+------------+------------+`
102			`\| 0 \| 0 / 27 ( 0%) \| - \| - \| - \|`
103			`\| 1 \| 0 / 33 ( 0%) \| - \| - \| - \|`
104			`\| 2 \| 0 / 32 ( 0%) \| - \| - \| - \|`
105			`\| 3 \| 14 / 33 ( 42%) \| 2.5V \| - \| - \|`
106			`\| 6 \| 1 / 33 ( 3%) \| 2.5V \| - \| - \|`
107			`\| 7 \| 0 / 32 ( 0%) \| - \| - \| - \|`
108			`\| 8 \| 1 / 13 ( 7%) \| 2.5V \| - \| - \|`
109			`+----------+----------------+------------+------------+------------+`
110
111			`Total placer CPU time: 3 secs`
112
113			`Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.`
114
115			`INFO - par: The routing stage will be skipped since the design contains no signals and/or connections.`
116			`Timing score: 0`
117
118			`Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.`
119
120
121			`All signals are completely routed.`
122
123
124			`PAR_SUMMARY::Run status = completed`
125			`PAR_SUMMARY::Number of unrouted conns = 0`
126			`PAR_SUMMARY::Worst slack> =`
127			`PAR_SUMMARY::Timing score> =`
128			`PAR_SUMMARY::Worst slack> =`
129			`PAR_SUMMARY::Timing score> =`
130			`PAR_SUMMARY::Number of errors = 0`
131
132			`Total CPU time to completion: 4 secs`
133			`Total REAL time to completion: 6 secs`
134
135			`par done!`
136
137			`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
138			`Copyright (c) 1995 AT&T Corp. All rights reserved.`
139			`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
140			`Copyright (c) 2001 Agere Systems All rights reserved.`
141			`Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.`

Browse

Tools

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.dir/] [5_1.par] - Blame information for rev 5