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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.dir/] [5_1_par.asd] - Blame information for rev 5

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Line No. Rev Author Line
1 5 liubenoff
[ActiveSupport PAR]
2
; # of global secondary clocks
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GLOBAL_SECONDARY_USED = 0;
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; I/O Bank 0 Usage
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BANK_0_USED = 0;
6
BANK_0_AVAIL = 27;
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BANK_0_VCCIO = NA;
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BANK_0_VREF1 = NA;
9
BANK_0_VREF2 = NA;
10
; I/O Bank 1 Usage
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BANK_1_USED = 0;
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BANK_1_AVAIL = 33;
13
BANK_1_VCCIO = NA;
14
BANK_1_VREF1 = NA;
15
BANK_1_VREF2 = NA;
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; I/O Bank 2 Usage
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BANK_2_USED = 0;
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BANK_2_AVAIL = 32;
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BANK_2_VCCIO = NA;
20
BANK_2_VREF1 = NA;
21
BANK_2_VREF2 = NA;
22
; I/O Bank 3 Usage
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BANK_3_USED = 14;
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BANK_3_AVAIL = 33;
25
BANK_3_VCCIO = 2.5V;
26
BANK_3_VREF1 = NA;
27
BANK_3_VREF2 = NA;
28
; I/O Bank 6 Usage
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BANK_6_USED = 1;
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BANK_6_AVAIL = 33;
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BANK_6_VCCIO = 2.5V;
32
BANK_6_VREF1 = NA;
33
BANK_6_VREF2 = NA;
34
; I/O Bank 7 Usage
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BANK_7_USED = 0;
36
BANK_7_AVAIL = 32;
37
BANK_7_VCCIO = NA;
38
BANK_7_VREF1 = NA;
39
BANK_7_VREF2 = NA;
40
; I/O Bank 8 Usage
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BANK_8_USED = 1;
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BANK_8_AVAIL = 13;
43
BANK_8_VCCIO = 2.5V;
44
BANK_8_VREF1 = NA;
45
BANK_8_VREF2 = NA;

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