URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.mrp] - Blame information for rev 5

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     Lattice Mapping Report File for Design Module 'DisplayDriverWrapper'
 
 
Design Information
------------------
 
Command line:   map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial
     DisplayDriverwDecoder_impl1.ngd -o DisplayDriverwDecoder_impl1_map.ncd -pr
     DisplayDriverwDecoder_impl1.prf -mp DisplayDriverwDecoder_impl1.mrp -lpf C:
     /Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_B
     uild/impl1/DisplayDriverwDecoder_impl1_synplify.lpf -lpf C:/Projects/single
     -14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriv
     erwDecoder.lpf -gui -msgset C:/Projects/single-14-segment-display-driver-w-
     decoder/Project/Lattice_FPGA_Build/promote.xml
Target Vendor:  LATTICE
Target Device:  LFE5UM5G-45FCABGA381
Target Performance:   8
Mapper:  sa5p00g,  version:  Diamond (64-bit) 3.8.0.115.3
Mapped on:  01/13/17  00:54:48
 
Design Summary
--------------
 
   Number of registers:      0 out of 44457 (0%)
      PFU registers:            0 out of 43848 (0%)
      PIO registers:            0 out of   609 (0%)
   Number of SLICEs:         0 out of 21924 (0%)
      SLICEs as Logic/ROM:      0 out of 21924 (0%)
      SLICEs as RAM:            0 out of 16443 (0%)
      SLICEs as Carry:          0 out of 21924 (0%)
   Number of LUT4s:          0 out of 43848 (0%)
      Number used as logic LUTs:          0
      Number used as distributed RAM:     0
      Number used as ripple logic:        0
      Number used as shift registers:     0
   Number of PIO sites used: 16 out of 203 (8%)
   Number of block RAMs:  0 out of 108 (0%)
   Number of GSRs:  0 out of 1 (0%)
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   DTR used :   No
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSOB):  0 out of 4 (0%)
   Number of DCC:  0 out of 60 (0%)
   Number of DCS:  0 out of 2 (0%)
   Number of PLLs:  0 out of 4 (0%)
   Number of DDRDLLs:  0 out of 4 (0%)
   Number of CLKDIV:  0 out of 4 (0%)
   Number of ECLKSYNC:  0 out of 10 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Number of DCUs:  0 out of 2 (0%)
   Number of DCU Channels:  0 out of 4 (0%)
   Number of EXTREFs:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
 
 
                                    Page 1
 
 
 
 
Design:  DisplayDriverWrapper                          Date:  01/13/17  00:54:48
 
Design Summary (cont)
---------------------
        Number Of Mapped DSP Components:
   --------------------------------
   MULT18X18D          0
   MULT9X9D            0
   ALU54B              0
   ALU24B              0
   PRADD18A            0
   PRADD9A             0
   --------------------------------
   Number of Used DSP MULT Sites:  0 out of 144 (0 %)
   Number of Used DSP ALU Sites:  0 out of 72 (0 %)
   Number of Used DSP PRADD Sites:  0 out of 144 (0 %)
   Number of clocks:  0
   Number of Clock Enables:  0
   Number of LSRs:  0
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
 
 
 
 
   Number of warnings:  1
   Number of errors:    0
 
 
Design Errors/Warnings
----------------------
 
WARNING - map: IO buffer missing for top level port button...logic will be
     discarded.
 
IO (PIO) Attributes
-------------------
 
+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| disp_data[0]        | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_sel            | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[14]       | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[13]       | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[12]       | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[11]       | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[10]       | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[9]        | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[8]        | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
 
                                    Page 2
 
 
 
 
Design:  DisplayDriverWrapper                          Date:  01/13/17  00:54:48
 
IO (PIO) Attributes (cont)
--------------------------
| disp_data[7]        | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[6]        | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[5]        | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[4]        | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[3]        | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[2]        | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data[1]        | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
 
Removed logic
-------------
 
Block GSR_INST undriven or does not drive anything - clipped.
Block rst_pad undriven or does not drive anything - clipped.
Block DDwD_Top/VCC undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped.
Block DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped.
Block clk_pad undriven or does not drive anything - clipped.
Signal GND undriven or does not drive anything - clipped.
Signal VCC undriven or does not drive anything - clipped.
Signal rst undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped.
Signal rst_c undriven or does not drive anything - clipped.
Signal DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped.
Signal clk_c undriven or does not drive anything - clipped.
Signal clk undriven or does not drive anything - clipped.
Block GND was optimized away.
Block VCC was optimized away.
 
Memory Usage
------------
 
 
 
 
 
 
 
 
                                    Page 3
 
 
 
 
Design:  DisplayDriverWrapper                          Date:  01/13/17  00:54:48
 
Run Time and Memory Usage
-------------------------
 
   Total CPU Time: 0 secs
   Total REAL Time: 0 secs
   Peak Memory Usage: 60 MB
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
                                    Page 4
 
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
     Copyright (c) 2001 Agere Systems   All rights reserved.
     Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights
     reserved.

Browse

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.mrp] - Blame information for rev 5

Line No.	Rev	Author	Line
1	5	liubenoff
2			`Lattice Mapping Report File for Design Module 'DisplayDriverWrapper'`
3
4
5			`Design Information`
6			`------------------`
7
8			`Command line: map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial`
9			`DisplayDriverwDecoder_impl1.ngd -o DisplayDriverwDecoder_impl1_map.ncd -pr`
10			`DisplayDriverwDecoder_impl1.prf -mp DisplayDriverwDecoder_impl1.mrp -lpf C:`
11			`/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_B`
12			`uild/impl1/DisplayDriverwDecoder_impl1_synplify.lpf -lpf C:/Projects/single`
13			`-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriv`
14			`erwDecoder.lpf -gui -msgset C:/Projects/single-14-segment-display-driver-w-`
15			`decoder/Project/Lattice_FPGA_Build/promote.xml`
16			`Target Vendor: LATTICE`
17			`Target Device: LFE5UM5G-45FCABGA381`
18			`Target Performance: 8`
19			`Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3`
20			`Mapped on: 01/13/17 00:54:48`
21
22			`Design Summary`
23			`--------------`
24
25			`Number of registers: 0 out of 44457 (0%)`
26			`PFU registers: 0 out of 43848 (0%)`
27			`PIO registers: 0 out of 609 (0%)`
28			`Number of SLICEs: 0 out of 21924 (0%)`
29			`SLICEs as Logic/ROM: 0 out of 21924 (0%)`
30			`SLICEs as RAM: 0 out of 16443 (0%)`
31			`SLICEs as Carry: 0 out of 21924 (0%)`
32			`Number of LUT4s: 0 out of 43848 (0%)`
33			`Number used as logic LUTs: 0`
34			`Number used as distributed RAM: 0`
35			`Number used as ripple logic: 0`
36			`Number used as shift registers: 0`
37			`Number of PIO sites used: 16 out of 203 (8%)`
38			`Number of block RAMs: 0 out of 108 (0%)`
39			`Number of GSRs: 0 out of 1 (0%)`
40			`JTAG used : No`
41			`Readback used : No`
42			`Oscillator used : No`
43			`Startup used : No`
44			`DTR used : No`
45			`Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)`
46			`Number of Dynamic Bank Controller (BCLVDSOB): 0 out of 4 (0%)`
47			`Number of DCC: 0 out of 60 (0%)`
48			`Number of DCS: 0 out of 2 (0%)`
49			`Number of PLLs: 0 out of 4 (0%)`
50			`Number of DDRDLLs: 0 out of 4 (0%)`
51			`Number of CLKDIV: 0 out of 4 (0%)`
52			`Number of ECLKSYNC: 0 out of 10 (0%)`
53			`Number of ECLKBRIDGECS: 0 out of 2 (0%)`
54			`Number of DCUs: 0 out of 2 (0%)`
55			`Number of DCU Channels: 0 out of 4 (0%)`
56			`Number of EXTREFs: 0 out of 2 (0%)`
57			`Notes:-`
58			`1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of`
59			`distributed RAMs) + 2*(Number of ripple logic)`
60			`2. Number of logic LUT4s does not include count of distributed RAM and`
61			`ripple logic.`
62
63
64			`Page 1`
65
66
67
68
69			`Design: DisplayDriverWrapper Date: 01/13/17 00:54:48`
70
71			`Design Summary (cont)`
72			`---------------------`
73			`Number Of Mapped DSP Components:`
74			`--------------------------------`
75			`MULT18X18D 0`
76			`MULT9X9D 0`
77			`ALU54B 0`
78			`ALU24B 0`
79			`PRADD18A 0`
80			`PRADD9A 0`
81			`--------------------------------`
82			`Number of Used DSP MULT Sites: 0 out of 144 (0 %)`
83			`Number of Used DSP ALU Sites: 0 out of 72 (0 %)`
84			`Number of Used DSP PRADD Sites: 0 out of 144 (0 %)`
85			`Number of clocks: 0`
86			`Number of Clock Enables: 0`
87			`Number of LSRs: 0`
88			`Number of nets driven by tri-state buffers: 0`
89			`Top 10 highest fanout non-clock nets:`
90
91
92
93
94			`Number of warnings: 1`
95			`Number of errors: 0`
96
97
98			`Design Errors/Warnings`
99			`----------------------`
100
101			`WARNING - map: IO buffer missing for top level port button...logic will be`
102			`discarded.`
103
104			`IO (PIO) Attributes`
105			`-------------------`
106
107			`+---------------------+-----------+-----------+------------+`
108			`\| IO Name \| Direction \| Levelmode \| IO \|`
109			`\| \| \| IO_TYPE \| Register \|`
110			`+---------------------+-----------+-----------+------------+`
111			`\| disp_data[0] \| OUTPUT \| LVCMOS25 \| \|`
112			`+---------------------+-----------+-----------+------------+`
113			`\| disp_sel \| OUTPUT \| LVCMOS25 \| \|`
114			`+---------------------+-----------+-----------+------------+`
115			`\| disp_data[14] \| OUTPUT \| LVCMOS25 \| \|`
116			`+---------------------+-----------+-----------+------------+`
117			`\| disp_data[13] \| OUTPUT \| LVCMOS25 \| \|`
118			`+---------------------+-----------+-----------+------------+`
119			`\| disp_data[12] \| OUTPUT \| LVCMOS25 \| \|`
120			`+---------------------+-----------+-----------+------------+`
121			`\| disp_data[11] \| OUTPUT \| LVCMOS25 \| \|`
122			`+---------------------+-----------+-----------+------------+`
123			`\| disp_data[10] \| OUTPUT \| LVCMOS25 \| \|`
124			`+---------------------+-----------+-----------+------------+`
125			`\| disp_data[9] \| OUTPUT \| LVCMOS25 \| \|`
126			`+---------------------+-----------+-----------+------------+`
127			`\| disp_data[8] \| OUTPUT \| LVCMOS25 \| \|`
128			`+---------------------+-----------+-----------+------------+`
129
130			`Page 2`
131
132
133
134
135			`Design: DisplayDriverWrapper Date: 01/13/17 00:54:48`
136
137			`IO (PIO) Attributes (cont)`
138			`--------------------------`
139			`\| disp_data[7] \| OUTPUT \| LVCMOS25 \| \|`
140			`+---------------------+-----------+-----------+------------+`
141			`\| disp_data[6] \| OUTPUT \| LVCMOS25 \| \|`
142			`+---------------------+-----------+-----------+------------+`
143			`\| disp_data[5] \| OUTPUT \| LVCMOS25 \| \|`
144			`+---------------------+-----------+-----------+------------+`
145			`\| disp_data[4] \| OUTPUT \| LVCMOS25 \| \|`
146			`+---------------------+-----------+-----------+------------+`
147			`\| disp_data[3] \| OUTPUT \| LVCMOS25 \| \|`
148			`+---------------------+-----------+-----------+------------+`
149			`\| disp_data[2] \| OUTPUT \| LVCMOS25 \| \|`
150			`+---------------------+-----------+-----------+------------+`
151			`\| disp_data[1] \| OUTPUT \| LVCMOS25 \| \|`
152			`+---------------------+-----------+-----------+------------+`
153
154			`Removed logic`
155			`-------------`
156
157			`Block GSR_INST undriven or does not drive anything - clipped.`
158			`Block rst_pad undriven or does not drive anything - clipped.`
159			`Block DDwD_Top/VCC undriven or does not drive anything - clipped.`
160			`Block DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped.`
161			`Block DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped.`
162			`Block DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped.`
163			`Block DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped.`
164			`Block DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped.`
165			`Block DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped.`
166			`Block DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped.`
167			`Block DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped.`
168			`Block clk_pad undriven or does not drive anything - clipped.`
169			`Signal GND undriven or does not drive anything - clipped.`
170			`Signal VCC undriven or does not drive anything - clipped.`
171			`Signal rst undriven or does not drive anything - clipped.`
172			`Signal DDwD_Top/ascii_reg[5] undriven or does not drive anything - clipped.`
173			`Signal DDwD_Top/ascii_reg[4] undriven or does not drive anything - clipped.`
174			`Signal DDwD_Top/ascii_reg[3] undriven or does not drive anything - clipped.`
175			`Signal DDwD_Top/ascii_reg[2] undriven or does not drive anything - clipped.`
176			`Signal DDwD_Top/ascii_reg[1] undriven or does not drive anything - clipped.`
177			`Signal DDwD_Top/ascii_reg[0] undriven or does not drive anything - clipped.`
178			`Signal DDwD_Top/ascii_reg[7] undriven or does not drive anything - clipped.`
179			`Signal rst_c undriven or does not drive anything - clipped.`
180			`Signal DDwD_Top/ascii_reg[6] undriven or does not drive anything - clipped.`
181			`Signal clk_c undriven or does not drive anything - clipped.`
182			`Signal clk undriven or does not drive anything - clipped.`
183			`Block GND was optimized away.`
184			`Block VCC was optimized away.`
185
186			`Memory Usage`
187			`------------`
188
189
190
191
192
193
194
195
196			`Page 3`
197
198
199
200
201			`Design: DisplayDriverWrapper Date: 01/13/17 00:54:48`
202
203			`Run Time and Memory Usage`
204			`-------------------------`
205
206			`Total CPU Time: 0 secs`
207			`Total REAL Time: 0 secs`
208			`Peak Memory Usage: 60 MB`
209
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262			`Page 4`
263
264
265			`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
266			`Copyright (c) 1995 AT&T Corp. All rights reserved.`
267			`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
268			`Copyright (c) 2001 Agere Systems All rights reserved.`
269			`Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights`
270			`reserved.`