URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.par] - Blame information for rev 5

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PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
Fri Jan 13 00:54:53 2017
 
C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
DisplayDriverwDecoder_impl1.prf -gui -msgset
C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml
 
 
Preference file: DisplayDriverwDecoder_impl1.prf.
 
Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            -            -            -            -            06           Complete
 
 
* : Design saved.
 
Total (real) run time for 1-seed: 6 secs
 
par done!
 
Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
Fri Jan 13 00:54:53 2017
 
PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
Preference file: DisplayDriverwDecoder_impl1.prf.
Placement level-cost: 5-1.
Routing Iterations: 6
 
Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.
Design name: DisplayDriverWrapper
NCD version: 3.3
Vendor:      LATTICE
Device:      LFE5UM5G-45F
Package:     CABGA381
Performance: 8
Loading device for application par from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status:                     Final          Version 1.36.
Performance Hardware Data Status:   Final          Version 50.1.
License checked out.
 
 
Ignore Preference Error(s):  True
Device utilization summary:
 
   PIO (prelim)      16/245           6% used
                     16/203           7% bonded
 
   SLICE              0/21924         0% used
 
 
 
Number of Signals: 0
Number of Connections: 0
 
Pin Constraint Summary:
   16 out of 16 pins locked (100% locked).
 
 
No signal is selected as Global Set/Reset.
Starting Placer Phase 0.
 
Finished Placer Phase 0.  REAL time: 5 secs
 
Starting Placer Phase 1.
 
Placer score = 0.
Finished Placer Phase 1.  REAL time: 5 secs
 
Starting Placer Phase 2.
.
Placer score =  0
Finished Placer Phase 2.  REAL time: 5 secs
 
 
------------------ Clock Report ------------------
 
Global Clock Resources:
  CLK_PIN    : 0 out of 12 (0%)
  GR_PCLK    : 0 out of 12 (0%)
  PLL        : 0 out of 4 (0%)
  DCS        : 0 out of 2 (0%)
  DCC        : 0 out of 60 (0%)
  CLKDIV     : 0 out of 4 (0%)
 
Quadrant TL Clocks:
 
  PRIMARY  : 0 out of 16 (0%)
 
Quadrant TR Clocks:
 
  PRIMARY  : 0 out of 16 (0%)
 
Quadrant BL Clocks:
 
  PRIMARY  : 0 out of 16 (0%)
 
Quadrant BR Clocks:
 
  PRIMARY  : 0 out of 16 (0%)
 
Edge Clocks:
 
  No edge clock selected.
 
 
--------------- End of Clock Report ---------------
 
 
+
I/O Usage Summary (final):
   16 out of 245 (6.5%) PIO sites used.
   16 out of 203 (7.9%) bonded PIO sites used.
   Number of PIO comps: 16; differential: 0.
   Number of Vref pins used: 0.
 
I/O Bank Usage Summary:
+----------+----------------+------------+------------+------------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
+----------+----------------+------------+------------+------------+
| 0        | 0 / 27 (  0%)  | -          | -          | -          |
| 1        | 0 / 33 (  0%)  | -          | -          | -          |
| 2        | 0 / 32 (  0%)  | -          | -          | -          |
| 3        | 14 / 33 ( 42%) | 2.5V       | -          | -          |
| 6        | 1 / 33 (  3%)  | 2.5V       | -          | -          |
| 7        | 0 / 32 (  0%)  | -          | -          | -          |
| 8        | 1 / 13 (  7%)  | 2.5V       | -          | -          |
+----------+----------------+------------+------------+------------+
 
Total placer CPU time: 3 secs
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
INFO - par: The routing stage will be skipped since the design contains no signals and/or connections.
Timing score: 0
 
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
 
 
All signals are completely routed.
 
 
PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack> = 
PAR_SUMMARY::Timing score> = 
PAR_SUMMARY::Worst  slack> = 
PAR_SUMMARY::Timing score> = 
PAR_SUMMARY::Number of errors = 0
 
Total CPU  time to completion: 4 secs
Total REAL time to completion: 6 secs
 
par done!
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.

Line No.	Rev	Author	Line
1	5	liubenoff	`PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.`
2			`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
3			`Copyright (c) 1995 AT&T Corp. All rights reserved.`
4			`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
5			`Copyright (c) 2001 Agere Systems All rights reserved.`
6			`Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.`
7			`Fri Jan 13 00:54:53 2017`
8
9			`C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t`
10			`DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir`
11			`DisplayDriverwDecoder_impl1.prf -gui -msgset`
12			`C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml`
13
14
15			`Preference file: DisplayDriverwDecoder_impl1.prf.`
16
17			`Level/ Number Worst Timing Worst Timing Run NCD`
18			`Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status`
19			`---------- -------- ----- ------ ----------- ----------- ---- ------`
20			`5_1 * 0 - - - - 06 Complete`
21
22
23			`* : Design saved.`
24
25			`Total (real) run time for 1-seed: 6 secs`
26
27			`par done!`
28
29			`Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"`
30			`Fri Jan 13 00:54:53 2017`
31
32			`PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.`
33			`Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf`
34			`Preference file: DisplayDriverwDecoder_impl1.prf.`
35			`Placement level-cost: 5-1.`
36			`Routing Iterations: 6`
37
38			`Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.`
39			`Design name: DisplayDriverWrapper`
40			`NCD version: 3.3`
41			`Vendor: LATTICE`
42			`Device: LFE5UM5G-45F`
43			`Package: CABGA381`
44			`Performance: 8`
45			`Loading device for application par from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.`
46			`Package Status: Final Version 1.36.`
47			`Performance Hardware Data Status: Final Version 50.1.`
48			`License checked out.`
49
50
51			`Ignore Preference Error(s): True`
52			`Device utilization summary:`
53
54			`PIO (prelim) 16/245 6% used`
55			`16/203 7% bonded`
56
57			`SLICE 0/21924 0% used`
58
59
60
61			`Number of Signals: 0`
62			`Number of Connections: 0`
63
64			`Pin Constraint Summary:`
65			`16 out of 16 pins locked (100% locked).`
66
67
68			`No signal is selected as Global Set/Reset.`
69			`Starting Placer Phase 0.`
70
71			`Finished Placer Phase 0. REAL time: 5 secs`
72
73			`Starting Placer Phase 1.`
74
75			`Placer score = 0.`
76			`Finished Placer Phase 1. REAL time: 5 secs`
77
78			`Starting Placer Phase 2.`
79			`.`
80			`Placer score = 0`
81			`Finished Placer Phase 2. REAL time: 5 secs`
82
83
84			`------------------ Clock Report ------------------`
85
86			`Global Clock Resources:`
87			`CLK_PIN : 0 out of 12 (0%)`
88			`GR_PCLK : 0 out of 12 (0%)`
89			`PLL : 0 out of 4 (0%)`
90			`DCS : 0 out of 2 (0%)`
91			`DCC : 0 out of 60 (0%)`
92			`CLKDIV : 0 out of 4 (0%)`
93
94			`Quadrant TL Clocks:`
95
96			`PRIMARY : 0 out of 16 (0%)`
97
98			`Quadrant TR Clocks:`
99
100			`PRIMARY : 0 out of 16 (0%)`
101
102			`Quadrant BL Clocks:`
103
104			`PRIMARY : 0 out of 16 (0%)`
105
106			`Quadrant BR Clocks:`
107
108			`PRIMARY : 0 out of 16 (0%)`
109
110			`Edge Clocks:`
111
112			`No edge clock selected.`
113
114
115			`--------------- End of Clock Report ---------------`
116
117
118			`+`
119			`I/O Usage Summary (final):`
120			`16 out of 245 (6.5%) PIO sites used.`
121			`16 out of 203 (7.9%) bonded PIO sites used.`
122			`Number of PIO comps: 16; differential: 0.`
123			`Number of Vref pins used: 0.`
124
125			`I/O Bank Usage Summary:`
126			`+----------+----------------+------------+------------+------------+`
127			`\| I/O Bank \| Usage \| Bank Vccio \| Bank Vref1 \| Bank Vref2 \|`
128			`+----------+----------------+------------+------------+------------+`
129			`\| 0 \| 0 / 27 ( 0%) \| - \| - \| - \|`
130			`\| 1 \| 0 / 33 ( 0%) \| - \| - \| - \|`
131			`\| 2 \| 0 / 32 ( 0%) \| - \| - \| - \|`
132			`\| 3 \| 14 / 33 ( 42%) \| 2.5V \| - \| - \|`
133			`\| 6 \| 1 / 33 ( 3%) \| 2.5V \| - \| - \|`
134			`\| 7 \| 0 / 32 ( 0%) \| - \| - \| - \|`
135			`\| 8 \| 1 / 13 ( 7%) \| 2.5V \| - \| - \|`
136			`+----------+----------------+------------+------------+------------+`
137
138			`Total placer CPU time: 3 secs`
139
140			`Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.`
141
142			`INFO - par: The routing stage will be skipped since the design contains no signals and/or connections.`
143			`Timing score: 0`
144
145			`Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.`
146
147
148			`All signals are completely routed.`
149
150
151			`PAR_SUMMARY::Run status = completed`
152			`PAR_SUMMARY::Number of unrouted conns = 0`
153			`PAR_SUMMARY::Worst slack> =`
154			`PAR_SUMMARY::Timing score> =`
155			`PAR_SUMMARY::Worst slack> =`
156			`PAR_SUMMARY::Timing score> =`
157			`PAR_SUMMARY::Number of errors = 0`
158
159			`Total CPU time to completion: 4 secs`
160			`Total REAL time to completion: 6 secs`
161
162			`par done!`
163
164			`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
165			`Copyright (c) 1995 AT&T Corp. All rights reserved.`
166			`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
167			`Copyright (c) 2001 Agere Systems All rights reserved.`
168			`Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.`

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.par] - Blame information for rev 5