| 1 |
5 |
liubenoff |
PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
|
| 2 |
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
| 3 |
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
| 4 |
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
| 5 |
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
| 6 |
|
|
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
|
| 7 |
9 |
liubenoff |
Wed Jan 18 01:08:29 2017
|
| 8 |
5 |
liubenoff |
|
| 9 |
|
|
C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
|
| 10 |
|
|
DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
|
| 11 |
|
|
DisplayDriverwDecoder_impl1.prf -gui -msgset
|
| 12 |
|
|
C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml
|
| 13 |
|
|
|
| 14 |
|
|
|
| 15 |
|
|
Preference file: DisplayDriverwDecoder_impl1.prf.
|
| 16 |
|
|
|
| 17 |
|
|
Level/ Number Worst Timing Worst Timing Run NCD
|
| 18 |
|
|
Cost [ncd] Unrouted Slack Score Slack(hold) Score(hold) Time Status
|
| 19 |
|
|
---------- -------- ----- ------ ----------- ----------- ---- ------
|
| 20 |
9 |
liubenoff |
5_1 * 0 -1.238 7103 0.178 0 25 Complete
|
| 21 |
5 |
liubenoff |
|
| 22 |
|
|
|
| 23 |
|
|
* : Design saved.
|
| 24 |
|
|
|
| 25 |
9 |
liubenoff |
Total (real) run time for 1-seed: 25 secs
|
| 26 |
5 |
liubenoff |
|
| 27 |
|
|
par done!
|
| 28 |
|
|
|
| 29 |
|
|
Lattice Place and Route Report for Design "DisplayDriverwDecoder_impl1_map.ncd"
|
| 30 |
9 |
liubenoff |
Wed Jan 18 01:08:29 2017
|
| 31 |
5 |
liubenoff |
|
| 32 |
|
|
PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
|
| 33 |
|
|
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
|
| 34 |
|
|
Preference file: DisplayDriverwDecoder_impl1.prf.
|
| 35 |
|
|
Placement level-cost: 5-1.
|
| 36 |
|
|
Routing Iterations: 6
|
| 37 |
|
|
|
| 38 |
|
|
Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.
|
| 39 |
9 |
liubenoff |
Design name: display_driver_wrapper
|
| 40 |
5 |
liubenoff |
NCD version: 3.3
|
| 41 |
|
|
Vendor: LATTICE
|
| 42 |
|
|
Device: LFE5UM5G-45F
|
| 43 |
|
|
Package: CABGA381
|
| 44 |
|
|
Performance: 8
|
| 45 |
|
|
Loading device for application par from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
|
| 46 |
|
|
Package Status: Final Version 1.36.
|
| 47 |
|
|
Performance Hardware Data Status: Final Version 50.1.
|
| 48 |
|
|
License checked out.
|
| 49 |
|
|
|
| 50 |
|
|
|
| 51 |
|
|
Ignore Preference Error(s): True
|
| 52 |
|
|
Device utilization summary:
|
| 53 |
|
|
|
| 54 |
9 |
liubenoff |
PIO (prelim) 19/245 7% used
|
| 55 |
|
|
19/203 9% bonded
|
| 56 |
6 |
liubenoff |
IOLOGIC 1/245 <1% used
|
| 57 |
5 |
liubenoff |
|
| 58 |
6 |
liubenoff |
SLICE 65/21924 <1% used
|
| 59 |
5 |
liubenoff |
|
| 60 |
6 |
liubenoff |
GSR 1/1 100% used
|
| 61 |
5 |
liubenoff |
|
| 62 |
|
|
|
| 63 |
6 |
liubenoff |
Number of Signals: 131
|
| 64 |
|
|
Number of Connections: 657
|
| 65 |
5 |
liubenoff |
|
| 66 |
|
|
Pin Constraint Summary:
|
| 67 |
9 |
liubenoff |
18 out of 18 pins locked (100% locked).
|
| 68 |
5 |
liubenoff |
|
| 69 |
6 |
liubenoff |
The following 1 signal is selected to use the primary clock routing resources:
|
| 70 |
|
|
clk_c (driver: clk, clk/ce/sr load #: 9/0/0)
|
| 71 |
5 |
liubenoff |
|
| 72 |
6 |
liubenoff |
|
| 73 |
|
|
Signal n_rst_c is selected as Global Set/Reset.
|
| 74 |
5 |
liubenoff |
Starting Placer Phase 0.
|
| 75 |
6 |
liubenoff |
.........
|
| 76 |
|
|
Finished Placer Phase 0. REAL time: 4 secs
|
| 77 |
5 |
liubenoff |
|
| 78 |
|
|
Starting Placer Phase 1.
|
| 79 |
6 |
liubenoff |
.......................
|
| 80 |
|
|
Placer score = 63578.
|
| 81 |
|
|
Finished Placer Phase 1. REAL time: 15 secs
|
| 82 |
5 |
liubenoff |
|
| 83 |
|
|
Starting Placer Phase 2.
|
| 84 |
|
|
.
|
| 85 |
6 |
liubenoff |
Placer score = 63553
|
| 86 |
|
|
Finished Placer Phase 2. REAL time: 15 secs
|
| 87 |
5 |
liubenoff |
|
| 88 |
|
|
|
| 89 |
|
|
------------------ Clock Report ------------------
|
| 90 |
|
|
|
| 91 |
|
|
Global Clock Resources:
|
| 92 |
|
|
CLK_PIN : 0 out of 12 (0%)
|
| 93 |
6 |
liubenoff |
GR_PCLK : 1 out of 12 (8%)
|
| 94 |
5 |
liubenoff |
PLL : 0 out of 4 (0%)
|
| 95 |
|
|
DCS : 0 out of 2 (0%)
|
| 96 |
|
|
DCC : 0 out of 60 (0%)
|
| 97 |
|
|
CLKDIV : 0 out of 4 (0%)
|
| 98 |
|
|
|
| 99 |
|
|
Quadrant TL Clocks:
|
| 100 |
|
|
|
| 101 |
|
|
PRIMARY : 0 out of 16 (0%)
|
| 102 |
|
|
|
| 103 |
|
|
Quadrant TR Clocks:
|
| 104 |
|
|
|
| 105 |
|
|
PRIMARY : 0 out of 16 (0%)
|
| 106 |
|
|
|
| 107 |
|
|
Quadrant BL Clocks:
|
| 108 |
6 |
liubenoff |
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 1
|
| 109 |
5 |
liubenoff |
|
| 110 |
6 |
liubenoff |
PRIMARY : 1 out of 16 (6%)
|
| 111 |
5 |
liubenoff |
|
| 112 |
|
|
Quadrant BR Clocks:
|
| 113 |
6 |
liubenoff |
PRIMARY "clk_c" from comp "clk" on PIO site "P3 (PL68C)", CLK/CE/SR load = 8
|
| 114 |
5 |
liubenoff |
|
| 115 |
6 |
liubenoff |
PRIMARY : 1 out of 16 (6%)
|
| 116 |
5 |
liubenoff |
|
| 117 |
|
|
Edge Clocks:
|
| 118 |
|
|
|
| 119 |
|
|
No edge clock selected.
|
| 120 |
|
|
|
| 121 |
|
|
|
| 122 |
|
|
--------------- End of Clock Report ---------------
|
| 123 |
|
|
|
| 124 |
|
|
|
| 125 |
|
|
+
|
| 126 |
|
|
I/O Usage Summary (final):
|
| 127 |
9 |
liubenoff |
19 out of 245 (7.8%) PIO sites used.
|
| 128 |
|
|
19 out of 203 (9.4%) bonded PIO sites used.
|
| 129 |
|
|
Number of PIO comps: 18; differential: 1.
|
| 130 |
5 |
liubenoff |
Number of Vref pins used: 0.
|
| 131 |
|
|
|
| 132 |
|
|
I/O Bank Usage Summary:
|
| 133 |
|
|
+----------+----------------+------------+------------+------------+
|
| 134 |
|
|
| I/O Bank | Usage | Bank Vccio | Bank Vref1 | Bank Vref2 |
|
| 135 |
|
|
+----------+----------------+------------+------------+------------+
|
| 136 |
|
|
| 0 | 0 / 27 ( 0%) | - | - | - |
|
| 137 |
|
|
| 1 | 0 / 33 ( 0%) | - | - | - |
|
| 138 |
6 |
liubenoff |
| 2 | 1 / 32 ( 3%) | 2.5V | - | - |
|
| 139 |
5 |
liubenoff |
| 3 | 14 / 33 ( 42%) | 2.5V | - | - |
|
| 140 |
9 |
liubenoff |
| 6 | 2 / 33 ( 6%) | 1.2V | - | - |
|
| 141 |
5 |
liubenoff |
| 7 | 0 / 32 ( 0%) | - | - | - |
|
| 142 |
6 |
liubenoff |
| 8 | 2 / 13 ( 15%) | 2.5V | - | - |
|
| 143 |
5 |
liubenoff |
+----------+----------------+------------+------------+------------+
|
| 144 |
|
|
|
| 145 |
9 |
liubenoff |
Total placer CPU time: 14 secs
|
| 146 |
5 |
liubenoff |
|
| 147 |
|
|
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
|
| 148 |
|
|
|
| 149 |
6 |
liubenoff |
|
| 150 |
|
|
Starting router resource preassignment
|
| 151 |
5 |
liubenoff |
|
| 152 |
9 |
liubenoff |
Completed router resource preassignment. Real time: 22 secs
|
| 153 |
6 |
liubenoff |
|
| 154 |
9 |
liubenoff |
Start NBR router at 01:08:51 01/18/17
|
| 155 |
6 |
liubenoff |
|
| 156 |
|
|
*****************************************************************
|
| 157 |
|
|
Info: NBR allows conflicts(one node used by more than one signal)
|
| 158 |
|
|
in the earlier iterations. In each iteration, it tries to
|
| 159 |
|
|
solve the conflicts while keeping the critical connections
|
| 160 |
|
|
routed as short as possible. The routing process is said to
|
| 161 |
|
|
be completed when no conflicts exist and all connections
|
| 162 |
|
|
are routed.
|
| 163 |
|
|
Note: NBR uses a different method to calculate timing slacks. The
|
| 164 |
|
|
worst slack and total negative slack may not be the same as
|
| 165 |
|
|
that in TRCE report. You should always run TRCE to verify
|
| 166 |
|
|
your design.
|
| 167 |
|
|
*****************************************************************
|
| 168 |
|
|
|
| 169 |
9 |
liubenoff |
Start NBR special constraint process at 01:08:52 01/18/17
|
| 170 |
6 |
liubenoff |
|
| 171 |
9 |
liubenoff |
Start NBR section for initial routing at 01:08:52 01/18/17
|
| 172 |
6 |
liubenoff |
Level 1, iteration 1
|
| 173 |
|
|
0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score;
|
| 174 |
9 |
liubenoff |
Estimated worst slack/total negative slack: -1.227ns/-8.380ns; real time: 23 secs
|
| 175 |
6 |
liubenoff |
Level 2, iteration 1
|
| 176 |
|
|
0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score;
|
| 177 |
9 |
liubenoff |
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 23 secs
|
| 178 |
6 |
liubenoff |
Level 3, iteration 1
|
| 179 |
|
|
0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score;
|
| 180 |
9 |
liubenoff |
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 23 secs
|
| 181 |
6 |
liubenoff |
Level 4, iteration 1
|
| 182 |
|
|
5(0.00%) conflicts; 0(0.00%) untouched conn; 8800 (nbr) score;
|
| 183 |
9 |
liubenoff |
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 23 secs
|
| 184 |
6 |
liubenoff |
|
| 185 |
|
|
Info: Initial congestion level at 75% usage is 0
|
| 186 |
|
|
Info: Initial congestion area at 75% usage is 0 (0.00%)
|
| 187 |
|
|
|
| 188 |
9 |
liubenoff |
Start NBR section for normal routing at 01:08:53 01/18/17
|
| 189 |
6 |
liubenoff |
Level 1, iteration 1
|
| 190 |
|
|
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
|
| 191 |
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
| 192 |
|
|
Level 2, iteration 1
|
| 193 |
|
|
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
|
| 194 |
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
| 195 |
|
|
Level 3, iteration 1
|
| 196 |
|
|
0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
|
| 197 |
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
| 198 |
|
|
Level 4, iteration 1
|
| 199 |
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
|
| 200 |
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
| 201 |
|
|
|
| 202 |
9 |
liubenoff |
Start NBR section for performance tuning (iteration 1) at 01:08:53 01/18/17
|
| 203 |
6 |
liubenoff |
Level 4, iteration 1
|
| 204 |
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
|
| 205 |
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
| 206 |
|
|
|
| 207 |
9 |
liubenoff |
Start NBR section for re-routing at 01:08:53 01/18/17
|
| 208 |
6 |
liubenoff |
Level 4, iteration 1
|
| 209 |
|
|
0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
|
| 210 |
|
|
Estimated worst slack/total negative slack: -1.238ns/-8.800ns; real time: 24 secs
|
| 211 |
|
|
|
| 212 |
9 |
liubenoff |
Start NBR section for post-routing at 01:08:53 01/18/17
|
| 213 |
6 |
liubenoff |
|
| 214 |
|
|
End NBR router with 0 unrouted connection
|
| 215 |
|
|
|
| 216 |
|
|
NBR Summary
|
| 217 |
|
|
-----------
|
| 218 |
|
|
Number of unrouted connections : 0 (0.00%)
|
| 219 |
|
|
Number of connections with timing violations : 9 (1.37%)
|
| 220 |
|
|
Estimated worst slack : -1.238ns
|
| 221 |
|
|
Timing score : 7103
|
| 222 |
|
|
-----------
|
| 223 |
|
|
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
|
| 224 |
|
|
|
| 225 |
|
|
|
| 226 |
|
|
|
| 227 |
|
|
Total CPU time 24 secs
|
| 228 |
|
|
Total REAL time: 25 secs
|
| 229 |
|
|
Completely routed.
|
| 230 |
|
|
End of route. 657 routed (100.00%); 0 unrouted.
|
| 231 |
|
|
|
| 232 |
|
|
Hold time timing score: 0, hold timing errors: 0
|
| 233 |
|
|
|
| 234 |
|
|
Timing score: 7103
|
| 235 |
|
|
|
| 236 |
5 |
liubenoff |
Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
|
| 237 |
|
|
|
| 238 |
|
|
|
| 239 |
|
|
All signals are completely routed.
|
| 240 |
|
|
|
| 241 |
|
|
|
| 242 |
|
|
PAR_SUMMARY::Run status = completed
|
| 243 |
|
|
PAR_SUMMARY::Number of unrouted conns = 0
|
| 244 |
6 |
liubenoff |
PAR_SUMMARY::Worst slack> = -1.238
|
| 245 |
|
|
PAR_SUMMARY::Timing score> = 7.103
|
| 246 |
|
|
PAR_SUMMARY::Worst slack> = 0.178
|
| 247 |
|
|
PAR_SUMMARY::Timing score> = 0.000
|
| 248 |
5 |
liubenoff |
PAR_SUMMARY::Number of errors = 0
|
| 249 |
|
|
|
| 250 |
6 |
liubenoff |
Total CPU time to completion: 25 secs
|
| 251 |
|
|
Total REAL time to completion: 26 secs
|
| 252 |
5 |
liubenoff |
|
| 253 |
|
|
par done!
|
| 254 |
|
|
|
| 255 |
|
|
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
| 256 |
|
|
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
| 257 |
|
|
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
| 258 |
|
|
Copyright (c) 2001 Agere Systems All rights reserved.
|
| 259 |
|
|
Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
|
