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liubenoff |
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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# Fri Jan 13 00:54:37 2017
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#Implementation: impl1
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Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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VHDL syntax check successful!
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
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@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
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Post processing for work.displaydriverwdecoder_top.arch
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Post processing for work.displaydriverwrapper.arch
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Fri Jan 13 00:54:37 2017
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###########################################################]
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Fri Jan 13 00:54:37 2017
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Fri Jan 13 00:54:37 2017
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###########################################################]
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Fri Jan 13 00:54:39 2017
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###########################################################]
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Pre-mapping Report
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Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.03L-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@A: MF827 |No constraint file specified.
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@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt
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Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Clock Summary
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*****************
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Start Requested Requested Clock Clock Clock
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Clock Frequency Period Type Group Load
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-----------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 8
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=====================================================================================================
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@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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None
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Fri Jan 13 00:54:39 2017
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###########################################################]
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Map & Optimize Report
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Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.03L-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Available hyper_sources - for debug and ip models
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None Found
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@N: MT206 |Auto Constrain mode is enabled
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pass CPU time Worst Slack Luts / Registers
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------------------------------------------------------------
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Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
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Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@S |Clock Optimization Summary
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#### START OF CLOCK OPTIMIZATION REPORT #####[
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1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
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============================== Non-Gated/Non-Generated Clocks ===============================
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
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---------------------------------------------------------------------------------------------
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@K:CKID0001 clk port 8 DDwD_Top.ascii_reg[6]
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=============================================================================================
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##### END OF CLOCK OPTIMIZATION REPORT ######]
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Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
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Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
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Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
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Writing EDIF Netlist and constraint files
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@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
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L-2016.03L-1
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@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
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Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
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Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
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@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
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##### START OF TIMING REPORT #####[
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# Timing Report written on Fri Jan 13 00:54:42 2017
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#
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Top view: DisplayDriverWrapper
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Requested Frequency: 1220.4 MHz
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Wire load mode: top
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Paths requested: 5
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Constraint File(s):
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@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
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@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
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Performance Summary
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*******************
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Worst slack in design: -0.145
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Requested Estimated Requested Estimated Clock Clock
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Starting Clock Frequency Frequency Period Period Slack Type Group
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------------------------------------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|clk 1220.4 MHz 1037.3 MHz 0.819 0.964 -0.145 inferred Autoconstr_clkgroup_0
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====================================================================================================================================
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Clock Relationships
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*******************
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Clocks | rise to rise | fall to fall | rise to fall | fall to rise
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-------------------------------------------------------------------------------------------------------------------------------------------
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Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
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-------------------------------------------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 0.819 -0.145 | No paths - | No paths - | No paths -
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===========================================================================================================================================
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|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
| 286 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
| 287 |
|
|
|
| 288 |
|
|
|
| 289 |
|
|
|
| 290 |
|
|
Interface Information
|
| 291 |
|
|
*********************
|
| 292 |
|
|
|
| 293 |
|
|
No IO constraint found
|
| 294 |
|
|
|
| 295 |
|
|
|
| 296 |
|
|
|
| 297 |
|
|
====================================
|
| 298 |
|
|
Detailed Report for Clock: DisplayDriverWrapper|clk
|
| 299 |
|
|
====================================
|
| 300 |
|
|
|
| 301 |
|
|
|
| 302 |
|
|
|
| 303 |
|
|
Starting Points with Worst Slack
|
| 304 |
|
|
********************************
|
| 305 |
|
|
|
| 306 |
|
|
Starting Arrival
|
| 307 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 308 |
|
|
Clock
|
| 309 |
|
|
--------------------------------------------------------------------------------------------------------------
|
| 310 |
|
|
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[0] 0.753 -0.145
|
| 311 |
|
|
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[1] 0.753 -0.145
|
| 312 |
|
|
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[2] 0.753 -0.145
|
| 313 |
|
|
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[3] 0.753 -0.145
|
| 314 |
|
|
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[4] 0.753 -0.145
|
| 315 |
|
|
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[5] 0.753 -0.145
|
| 316 |
|
|
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX Q ascii_reg[6] 0.753 -0.145
|
| 317 |
|
|
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX Q ascii_reg[7] 0.753 -0.145
|
| 318 |
|
|
==============================================================================================================
|
| 319 |
|
|
|
| 320 |
|
|
|
| 321 |
|
|
Ending Points with Worst Slack
|
| 322 |
|
|
******************************
|
| 323 |
|
|
|
| 324 |
|
|
Starting Required
|
| 325 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 326 |
|
|
Clock
|
| 327 |
|
|
---------------------------------------------------------------------------------------------------------------
|
| 328 |
|
|
DDwD_Top.ascii_reg[0] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[0] 0.608 -0.145
|
| 329 |
|
|
DDwD_Top.ascii_reg[1] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[1] 0.608 -0.145
|
| 330 |
|
|
DDwD_Top.ascii_reg[2] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[2] 0.608 -0.145
|
| 331 |
|
|
DDwD_Top.ascii_reg[3] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[3] 0.608 -0.145
|
| 332 |
|
|
DDwD_Top.ascii_reg[4] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[4] 0.608 -0.145
|
| 333 |
|
|
DDwD_Top.ascii_reg[5] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[5] 0.608 -0.145
|
| 334 |
|
|
DDwD_Top.ascii_reg[6] DisplayDriverWrapper|clk FD1S3JX D ascii_reg[6] 0.608 -0.145
|
| 335 |
|
|
DDwD_Top.ascii_reg[7] DisplayDriverWrapper|clk FD1S3IX D ascii_reg[7] 0.608 -0.145
|
| 336 |
|
|
===============================================================================================================
|
| 337 |
|
|
|
| 338 |
|
|
|
| 339 |
|
|
|
| 340 |
|
|
Worst Path Information
|
| 341 |
|
|
***********************
|
| 342 |
|
|
|
| 343 |
|
|
|
| 344 |
|
|
Path information for path number 1:
|
| 345 |
|
|
Requested Period: 0.819
|
| 346 |
|
|
- Setup time: 0.211
|
| 347 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 348 |
|
|
= Required time: 0.608
|
| 349 |
|
|
|
| 350 |
|
|
- Propagation time: 0.753
|
| 351 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 352 |
|
|
= Slack (critical) : -0.145
|
| 353 |
|
|
|
| 354 |
|
|
Number of logic level(s): 0
|
| 355 |
|
|
Starting point: DDwD_Top.ascii_reg[0] / Q
|
| 356 |
|
|
Ending point: DDwD_Top.ascii_reg[0] / D
|
| 357 |
|
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 358 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 359 |
|
|
|
| 360 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 361 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 362 |
|
|
---------------------------------------------------------------------------------------
|
| 363 |
|
|
DDwD_Top.ascii_reg[0] FD1S3IX Q Out 0.753 0.753 -
|
| 364 |
|
|
ascii_reg[0] Net - - - - 1
|
| 365 |
|
|
DDwD_Top.ascii_reg[0] FD1S3IX D In 0.000 0.753 -
|
| 366 |
|
|
=======================================================================================
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
Path information for path number 2:
|
| 370 |
|
|
Requested Period: 0.819
|
| 371 |
|
|
- Setup time: 0.211
|
| 372 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 373 |
|
|
= Required time: 0.608
|
| 374 |
|
|
|
| 375 |
|
|
- Propagation time: 0.753
|
| 376 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 377 |
|
|
= Slack (critical) : -0.145
|
| 378 |
|
|
|
| 379 |
|
|
Number of logic level(s): 0
|
| 380 |
|
|
Starting point: DDwD_Top.ascii_reg[1] / Q
|
| 381 |
|
|
Ending point: DDwD_Top.ascii_reg[1] / D
|
| 382 |
|
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 383 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 384 |
|
|
|
| 385 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 386 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 387 |
|
|
---------------------------------------------------------------------------------------
|
| 388 |
|
|
DDwD_Top.ascii_reg[1] FD1S3JX Q Out 0.753 0.753 -
|
| 389 |
|
|
ascii_reg[1] Net - - - - 1
|
| 390 |
|
|
DDwD_Top.ascii_reg[1] FD1S3JX D In 0.000 0.753 -
|
| 391 |
|
|
=======================================================================================
|
| 392 |
|
|
|
| 393 |
|
|
|
| 394 |
|
|
Path information for path number 3:
|
| 395 |
|
|
Requested Period: 0.819
|
| 396 |
|
|
- Setup time: 0.211
|
| 397 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 398 |
|
|
= Required time: 0.608
|
| 399 |
|
|
|
| 400 |
|
|
- Propagation time: 0.753
|
| 401 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 402 |
|
|
= Slack (critical) : -0.145
|
| 403 |
|
|
|
| 404 |
|
|
Number of logic level(s): 0
|
| 405 |
|
|
Starting point: DDwD_Top.ascii_reg[2] / Q
|
| 406 |
|
|
Ending point: DDwD_Top.ascii_reg[2] / D
|
| 407 |
|
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 408 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 409 |
|
|
|
| 410 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 411 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 412 |
|
|
---------------------------------------------------------------------------------------
|
| 413 |
|
|
DDwD_Top.ascii_reg[2] FD1S3IX Q Out 0.753 0.753 -
|
| 414 |
|
|
ascii_reg[2] Net - - - - 1
|
| 415 |
|
|
DDwD_Top.ascii_reg[2] FD1S3IX D In 0.000 0.753 -
|
| 416 |
|
|
=======================================================================================
|
| 417 |
|
|
|
| 418 |
|
|
|
| 419 |
|
|
Path information for path number 4:
|
| 420 |
|
|
Requested Period: 0.819
|
| 421 |
|
|
- Setup time: 0.211
|
| 422 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 423 |
|
|
= Required time: 0.608
|
| 424 |
|
|
|
| 425 |
|
|
- Propagation time: 0.753
|
| 426 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 427 |
|
|
= Slack (critical) : -0.145
|
| 428 |
|
|
|
| 429 |
|
|
Number of logic level(s): 0
|
| 430 |
|
|
Starting point: DDwD_Top.ascii_reg[3] / Q
|
| 431 |
|
|
Ending point: DDwD_Top.ascii_reg[3] / D
|
| 432 |
|
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 433 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 434 |
|
|
|
| 435 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 436 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 437 |
|
|
---------------------------------------------------------------------------------------
|
| 438 |
|
|
DDwD_Top.ascii_reg[3] FD1S3IX Q Out 0.753 0.753 -
|
| 439 |
|
|
ascii_reg[3] Net - - - - 1
|
| 440 |
|
|
DDwD_Top.ascii_reg[3] FD1S3IX D In 0.000 0.753 -
|
| 441 |
|
|
=======================================================================================
|
| 442 |
|
|
|
| 443 |
|
|
|
| 444 |
|
|
Path information for path number 5:
|
| 445 |
|
|
Requested Period: 0.819
|
| 446 |
|
|
- Setup time: 0.211
|
| 447 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 448 |
|
|
= Required time: 0.608
|
| 449 |
|
|
|
| 450 |
|
|
- Propagation time: 0.753
|
| 451 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 452 |
|
|
= Slack (critical) : -0.145
|
| 453 |
|
|
|
| 454 |
|
|
Number of logic level(s): 0
|
| 455 |
|
|
Starting point: DDwD_Top.ascii_reg[4] / Q
|
| 456 |
|
|
Ending point: DDwD_Top.ascii_reg[4] / D
|
| 457 |
|
|
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 458 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 459 |
|
|
|
| 460 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 461 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 462 |
|
|
---------------------------------------------------------------------------------------
|
| 463 |
|
|
DDwD_Top.ascii_reg[4] FD1S3JX Q Out 0.753 0.753 -
|
| 464 |
|
|
ascii_reg[4] Net - - - - 1
|
| 465 |
|
|
DDwD_Top.ascii_reg[4] FD1S3JX D In 0.000 0.753 -
|
| 466 |
|
|
=======================================================================================
|
| 467 |
|
|
|
| 468 |
|
|
|
| 469 |
|
|
|
| 470 |
|
|
##### END OF TIMING REPORT #####]
|
| 471 |
|
|
|
| 472 |
|
|
Constraints that could not be applied
|
| 473 |
|
|
None
|
| 474 |
|
|
|
| 475 |
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
| 476 |
|
|
|
| 477 |
|
|
|
| 478 |
|
|
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
|
| 479 |
|
|
|
| 480 |
|
|
---------------------------------------
|
| 481 |
|
|
Resource Usage Report
|
| 482 |
|
|
Part: lfe5um5g_45f-8
|
| 483 |
|
|
|
| 484 |
|
|
Register bits: 8 of 43848 (0%)
|
| 485 |
|
|
PIC Latch: 0
|
| 486 |
|
|
I/O cells: 18
|
| 487 |
|
|
|
| 488 |
|
|
|
| 489 |
|
|
Details:
|
| 490 |
|
|
FD1S3IX: 5
|
| 491 |
|
|
FD1S3JX: 3
|
| 492 |
|
|
GSR: 1
|
| 493 |
|
|
IB: 2
|
| 494 |
|
|
OB: 16
|
| 495 |
|
|
PUR: 1
|
| 496 |
|
|
VHI: 2
|
| 497 |
|
|
VLO: 1
|
| 498 |
|
|
false: 1
|
| 499 |
|
|
Mapper successful!
|
| 500 |
|
|
|
| 501 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
|
| 502 |
|
|
|
| 503 |
|
|
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
|
| 504 |
|
|
# Fri Jan 13 00:54:42 2017
|
| 505 |
|
|
|
| 506 |
|
|
###########################################################]
|
