1 |
5 |
liubenoff |
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
|
2 |
|
|
#install: C:\lscc\diamond\3.8_x64\synpbase
|
3 |
|
|
#OS: Windows 8 6.2
|
4 |
|
|
#Hostname: DESKTOP-1AUKF7V
|
5 |
|
|
|
6 |
6 |
liubenoff |
# Tue Jan 17 01:19:09 2017
|
7 |
5 |
liubenoff |
|
8 |
|
|
#Implementation: impl1
|
9 |
|
|
|
10 |
|
|
Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
|
11 |
|
|
@N|Running in 64-bit mode
|
12 |
|
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
13 |
|
|
|
14 |
|
|
Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
|
15 |
|
|
@N|Running in 64-bit mode
|
16 |
|
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
17 |
|
|
|
18 |
|
|
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
19 |
|
|
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
|
20 |
6 |
liubenoff |
File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
|
21 |
|
|
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
|
22 |
5 |
liubenoff |
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
|
23 |
6 |
liubenoff |
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
|
24 |
5 |
liubenoff |
VHDL syntax check successful!
|
25 |
6 |
liubenoff |
|
26 |
|
|
Compiler output is up to date. No re-compile necessary
|
27 |
|
|
|
28 |
5 |
liubenoff |
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
|
29 |
|
|
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
|
30 |
|
|
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
|
31 |
6 |
liubenoff |
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
|
32 |
|
|
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
|
33 |
|
|
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
|
34 |
|
|
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
|
35 |
|
|
Post processing for work.rom128x1a.syn_black_box
|
36 |
|
|
Post processing for work.distromasciidecoder.structure
|
37 |
|
|
Post processing for work.asciidecoder.arch
|
38 |
5 |
liubenoff |
Post processing for work.displaydriverwdecoder_top.arch
|
39 |
|
|
Post processing for work.displaydriverwrapper.arch
|
40 |
6 |
liubenoff |
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
|
41 |
|
|
@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
|
42 |
|
|
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
|
43 |
|
|
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
|
44 |
|
|
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
|
45 |
5 |
liubenoff |
|
46 |
6 |
liubenoff |
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
|
47 |
5 |
liubenoff |
|
48 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
49 |
|
|
|
50 |
|
|
Process completed successfully.
|
51 |
6 |
liubenoff |
# Tue Jan 17 01:19:09 2017
|
52 |
5 |
liubenoff |
|
53 |
|
|
###########################################################]
|
54 |
|
|
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
|
55 |
|
|
@N|Running in 64-bit mode
|
56 |
|
|
|
57 |
|
|
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
58 |
|
|
|
59 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
60 |
|
|
|
61 |
|
|
Process completed successfully.
|
62 |
6 |
liubenoff |
# Tue Jan 17 01:19:09 2017
|
63 |
5 |
liubenoff |
|
64 |
|
|
###########################################################]
|
65 |
|
|
@END
|
66 |
|
|
|
67 |
|
|
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
68 |
|
|
|
69 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
70 |
|
|
|
71 |
|
|
Process completed successfully.
|
72 |
6 |
liubenoff |
# Tue Jan 17 01:19:09 2017
|
73 |
5 |
liubenoff |
|
74 |
|
|
###########################################################]
|
75 |
|
|
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
|
76 |
|
|
@N|Running in 64-bit mode
|
77 |
|
|
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
|
78 |
|
|
|
79 |
|
|
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
80 |
|
|
|
81 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
82 |
|
|
|
83 |
|
|
Process completed successfully.
|
84 |
6 |
liubenoff |
# Tue Jan 17 01:19:11 2017
|
85 |
5 |
liubenoff |
|
86 |
|
|
###########################################################]
|
87 |
|
|
Pre-mapping Report
|
88 |
|
|
|
89 |
|
|
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
|
90 |
|
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
91 |
|
|
Product Version L-2016.03L-1
|
92 |
|
|
|
93 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
94 |
|
|
|
95 |
|
|
@A: MF827 |No constraint file specified.
|
96 |
|
|
@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt
|
97 |
|
|
Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file
|
98 |
|
|
@N: MF248 |Running in 64-bit mode.
|
99 |
|
|
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
100 |
|
|
|
101 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
102 |
|
|
|
103 |
|
|
|
104 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
105 |
|
|
|
106 |
|
|
|
107 |
6 |
liubenoff |
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
|
108 |
5 |
liubenoff |
|
109 |
|
|
|
110 |
6 |
liubenoff |
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
|
111 |
5 |
liubenoff |
|
112 |
|
|
ICG Latch Removal Summary:
|
113 |
|
|
Number of ICG latches removed: 0
|
114 |
|
|
Number of ICG latches not removed: 0
|
115 |
|
|
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
|
116 |
|
|
|
117 |
|
|
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
118 |
|
|
|
119 |
|
|
|
120 |
|
|
|
121 |
|
|
Clock Summary
|
122 |
|
|
*****************
|
123 |
|
|
|
124 |
6 |
liubenoff |
Start Requested Requested Clock Clock Clock
|
125 |
|
|
Clock Frequency Period Type Group Load
|
126 |
|
|
--------------------------------------------------------------------------------------------------------
|
127 |
|
|
DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
|
128 |
|
|
========================================================================================================
|
129 |
5 |
liubenoff |
|
130 |
6 |
liubenoff |
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
131 |
5 |
liubenoff |
|
132 |
|
|
Finished Pre Mapping Phase.
|
133 |
|
|
|
134 |
|
|
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
135 |
|
|
|
136 |
|
|
None
|
137 |
|
|
None
|
138 |
|
|
|
139 |
|
|
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
140 |
|
|
|
141 |
|
|
Pre-mapping successful!
|
142 |
|
|
|
143 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
|
144 |
|
|
|
145 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
146 |
6 |
liubenoff |
# Tue Jan 17 01:19:11 2017
|
147 |
5 |
liubenoff |
|
148 |
|
|
###########################################################]
|
149 |
|
|
Map & Optimize Report
|
150 |
|
|
|
151 |
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
|
152 |
|
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
153 |
|
|
Product Version L-2016.03L-1
|
154 |
|
|
|
155 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
156 |
|
|
|
157 |
|
|
@N: MF248 |Running in 64-bit mode.
|
158 |
|
|
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
159 |
|
|
|
160 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
|
161 |
|
|
|
162 |
|
|
|
163 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
|
164 |
|
|
|
165 |
|
|
|
166 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
167 |
|
|
|
168 |
|
|
|
169 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
170 |
|
|
|
171 |
|
|
|
172 |
|
|
|
173 |
|
|
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
174 |
|
|
|
175 |
|
|
|
176 |
|
|
Available hyper_sources - for debug and ip models
|
177 |
|
|
None Found
|
178 |
|
|
|
179 |
|
|
@N: MT206 |Auto Constrain mode is enabled
|
180 |
|
|
|
181 |
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
182 |
|
|
|
183 |
6 |
liubenoff |
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
|
184 |
5 |
liubenoff |
|
185 |
|
|
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
186 |
|
|
|
187 |
|
|
|
188 |
|
|
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
189 |
|
|
|
190 |
|
|
|
191 |
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
192 |
|
|
|
193 |
|
|
|
194 |
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
195 |
|
|
|
196 |
|
|
|
197 |
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
198 |
|
|
|
199 |
|
|
|
200 |
|
|
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
201 |
|
|
|
202 |
|
|
|
203 |
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
204 |
|
|
|
205 |
|
|
|
206 |
|
|
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
210 |
|
|
|
211 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
212 |
|
|
------------------------------------------------------------
|
213 |
6 |
liubenoff |
1 0h:00m:00s -0.70ns 1 / 8
|
214 |
|
|
2 0h:00m:00s -0.70ns 1 / 8
|
215 |
|
|
@N: FX271 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Replicating instance symbol_scan_cntr[0] (in view: work.DisplayDriverWrapper(arch)) with 15 loads 1 time to improve timing.
|
216 |
|
|
Timing driven replication report
|
217 |
|
|
Added 1 Registers via timing driven replication
|
218 |
|
|
Added 0 LUTs via timing driven replication
|
219 |
5 |
liubenoff |
|
220 |
6 |
liubenoff |
3 0h:00m:00s -0.64ns 1 / 9
|
221 |
|
|
|
222 |
|
|
4 0h:00m:00s -0.64ns 1 / 9
|
223 |
|
|
|
224 |
5 |
liubenoff |
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
225 |
|
|
|
226 |
|
|
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
227 |
|
|
|
228 |
6 |
liubenoff |
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
229 |
5 |
liubenoff |
|
230 |
|
|
|
231 |
|
|
|
232 |
|
|
@S |Clock Optimization Summary
|
233 |
|
|
|
234 |
|
|
|
235 |
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
236 |
|
|
|
237 |
6 |
liubenoff |
1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
|
238 |
5 |
liubenoff |
|
239 |
|
|
|
240 |
|
|
|
241 |
6 |
liubenoff |
============================= Non-Gated/Non-Generated Clocks ==============================
|
242 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
243 |
|
|
-------------------------------------------------------------------------------------------
|
244 |
|
|
@K:CKID0001 button port 9 symbol_scan_cntr[0]
|
245 |
|
|
===========================================================================================
|
246 |
5 |
liubenoff |
|
247 |
|
|
|
248 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
249 |
|
|
|
250 |
|
|
|
251 |
|
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
|
252 |
|
|
|
253 |
|
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
|
254 |
|
|
|
255 |
6 |
liubenoff |
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
256 |
5 |
liubenoff |
|
257 |
|
|
Writing EDIF Netlist and constraint files
|
258 |
|
|
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
|
259 |
|
|
L-2016.03L-1
|
260 |
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
261 |
|
|
|
262 |
6 |
liubenoff |
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
|
263 |
5 |
liubenoff |
|
264 |
|
|
|
265 |
6 |
liubenoff |
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
266 |
5 |
liubenoff |
|
267 |
6 |
liubenoff |
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
|
268 |
5 |
liubenoff |
|
269 |
|
|
|
270 |
|
|
##### START OF TIMING REPORT #####[
|
271 |
6 |
liubenoff |
# Timing Report written on Tue Jan 17 01:19:13 2017
|
272 |
5 |
liubenoff |
#
|
273 |
|
|
|
274 |
|
|
|
275 |
|
|
Top view: DisplayDriverWrapper
|
276 |
6 |
liubenoff |
Requested Frequency: 443.5 MHz
|
277 |
5 |
liubenoff |
Wire load mode: top
|
278 |
|
|
Paths requested: 5
|
279 |
|
|
Constraint File(s):
|
280 |
|
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
281 |
|
|
|
282 |
|
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
283 |
|
|
|
284 |
|
|
|
285 |
|
|
|
286 |
|
|
Performance Summary
|
287 |
|
|
*******************
|
288 |
|
|
|
289 |
|
|
|
290 |
6 |
liubenoff |
Worst slack in design: -0.398
|
291 |
5 |
liubenoff |
|
292 |
6 |
liubenoff |
Requested Estimated Requested Estimated Clock Clock
|
293 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
294 |
|
|
-------------------------------------------------------------------------------------------------------------------------------------
|
295 |
|
|
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
|
296 |
|
|
=====================================================================================================================================
|
297 |
5 |
liubenoff |
|
298 |
|
|
|
299 |
|
|
|
300 |
|
|
|
301 |
|
|
|
302 |
|
|
Clock Relationships
|
303 |
|
|
*******************
|
304 |
|
|
|
305 |
6 |
liubenoff |
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
306 |
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------
|
307 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
308 |
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------
|
309 |
|
|
DisplayDriverWrapper|button DisplayDriverWrapper|button | 2.255 -0.398 | No paths - | No paths - | No paths -
|
310 |
|
|
=================================================================================================================================================
|
311 |
5 |
liubenoff |
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
312 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
313 |
|
|
|
314 |
|
|
|
315 |
|
|
|
316 |
|
|
Interface Information
|
317 |
|
|
*********************
|
318 |
|
|
|
319 |
|
|
No IO constraint found
|
320 |
|
|
|
321 |
|
|
|
322 |
|
|
|
323 |
|
|
====================================
|
324 |
6 |
liubenoff |
Detailed Report for Clock: DisplayDriverWrapper|button
|
325 |
5 |
liubenoff |
====================================
|
326 |
|
|
|
327 |
|
|
|
328 |
|
|
|
329 |
|
|
Starting Points with Worst Slack
|
330 |
|
|
********************************
|
331 |
|
|
|
332 |
6 |
liubenoff |
Starting Arrival
|
333 |
|
|
Instance Reference Type Pin Net Time Slack
|
334 |
|
|
Clock
|
335 |
|
|
--------------------------------------------------------------------------------------------------------------------------------
|
336 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[1] 0.933 -0.398
|
337 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
|
338 |
|
|
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[3] 0.933 -0.339
|
339 |
|
|
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
|
340 |
|
|
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[5] 0.933 -0.280
|
341 |
|
|
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
|
342 |
|
|
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
|
343 |
|
|
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
|
344 |
|
|
================================================================================================================================
|
345 |
5 |
liubenoff |
|
346 |
|
|
|
347 |
|
|
Ending Points with Worst Slack
|
348 |
|
|
******************************
|
349 |
|
|
|
350 |
6 |
liubenoff |
Starting Required
|
351 |
|
|
Instance Reference Type Pin Net Time Slack
|
352 |
|
|
Clock
|
353 |
|
|
------------------------------------------------------------------------------------------------------------------------------
|
354 |
|
|
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
|
355 |
|
|
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
|
356 |
|
|
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
|
357 |
|
|
symbol_scan_cntr[3] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[3] 2.044 -0.280
|
358 |
|
|
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[4] 2.044 -0.280
|
359 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
|
360 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
|
361 |
|
|
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
|
362 |
|
|
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
|
363 |
|
|
==============================================================================================================================
|
364 |
5 |
liubenoff |
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
Worst Path Information
|
368 |
|
|
***********************
|
369 |
|
|
|
370 |
|
|
|
371 |
|
|
Path information for path number 1:
|
372 |
6 |
liubenoff |
Requested Period: 2.255
|
373 |
5 |
liubenoff |
- Setup time: 0.211
|
374 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
375 |
6 |
liubenoff |
= Required time: 2.044
|
376 |
5 |
liubenoff |
|
377 |
6 |
liubenoff |
- Propagation time: 2.442
|
378 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
379 |
6 |
liubenoff |
= Slack (critical) : -0.398
|
380 |
5 |
liubenoff |
|
381 |
6 |
liubenoff |
Number of logic level(s): 4
|
382 |
|
|
Starting point: symbol_scan_cntr[1] / Q
|
383 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
384 |
|
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
385 |
|
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
386 |
5 |
liubenoff |
|
387 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
388 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
389 |
|
|
-------------------------------------------------------------------------------------------
|
390 |
|
|
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
|
391 |
|
|
symbol_scan_cntr[1] Net - - - - 15
|
392 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
393 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
394 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
395 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
396 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
397 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
398 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
399 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
400 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
401 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
402 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
403 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
404 |
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
|
405 |
|
|
===========================================================================================
|
406 |
5 |
liubenoff |
|
407 |
|
|
|
408 |
|
|
Path information for path number 2:
|
409 |
6 |
liubenoff |
Requested Period: 2.255
|
410 |
5 |
liubenoff |
- Setup time: 0.211
|
411 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
412 |
6 |
liubenoff |
= Required time: 2.044
|
413 |
5 |
liubenoff |
|
414 |
6 |
liubenoff |
- Propagation time: 2.442
|
415 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
416 |
6 |
liubenoff |
= Slack (critical) : -0.398
|
417 |
5 |
liubenoff |
|
418 |
6 |
liubenoff |
Number of logic level(s): 4
|
419 |
|
|
Starting point: symbol_scan_cntr[2] / Q
|
420 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
421 |
|
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
422 |
|
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
423 |
5 |
liubenoff |
|
424 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
425 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
426 |
|
|
-------------------------------------------------------------------------------------------
|
427 |
|
|
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
|
428 |
|
|
symbol_scan_cntr[2] Net - - - - 15
|
429 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
430 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
431 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
432 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
433 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
434 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
435 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
436 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
437 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
438 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
439 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
440 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
441 |
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
|
442 |
|
|
===========================================================================================
|
443 |
5 |
liubenoff |
|
444 |
|
|
|
445 |
|
|
Path information for path number 3:
|
446 |
6 |
liubenoff |
Requested Period: 2.255
|
447 |
5 |
liubenoff |
- Setup time: 0.211
|
448 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
449 |
6 |
liubenoff |
= Required time: 2.044
|
450 |
5 |
liubenoff |
|
451 |
6 |
liubenoff |
- Propagation time: 2.382
|
452 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
453 |
6 |
liubenoff |
= Slack (non-critical) : -0.339
|
454 |
5 |
liubenoff |
|
455 |
6 |
liubenoff |
Number of logic level(s): 3
|
456 |
|
|
Starting point: symbol_scan_cntr[3] / Q
|
457 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
458 |
|
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
459 |
|
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
460 |
5 |
liubenoff |
|
461 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
462 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
463 |
|
|
-------------------------------------------------------------------------------------------
|
464 |
|
|
symbol_scan_cntr[3] FD1S3DX Q Out 0.933 0.933 -
|
465 |
|
|
symbol_scan_cntr[3] Net - - - - 15
|
466 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
|
467 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
|
468 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
469 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
|
470 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
|
471 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
472 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
|
473 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
|
474 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
475 |
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
|
476 |
|
|
===========================================================================================
|
477 |
5 |
liubenoff |
|
478 |
|
|
|
479 |
|
|
Path information for path number 4:
|
480 |
6 |
liubenoff |
Requested Period: 2.255
|
481 |
5 |
liubenoff |
- Setup time: 0.211
|
482 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
483 |
6 |
liubenoff |
= Required time: 2.044
|
484 |
5 |
liubenoff |
|
485 |
6 |
liubenoff |
- Propagation time: 2.382
|
486 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
487 |
6 |
liubenoff |
= Slack (non-critical) : -0.339
|
488 |
5 |
liubenoff |
|
489 |
6 |
liubenoff |
Number of logic level(s): 3
|
490 |
|
|
Starting point: symbol_scan_cntr[4] / Q
|
491 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
492 |
|
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
493 |
|
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
494 |
5 |
liubenoff |
|
495 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
496 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
497 |
|
|
-------------------------------------------------------------------------------------------
|
498 |
|
|
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
|
499 |
|
|
symbol_scan_cntr[4] Net - - - - 15
|
500 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
|
501 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
|
502 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
503 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
|
504 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
|
505 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
506 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
|
507 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
|
508 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
509 |
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
|
510 |
|
|
===========================================================================================
|
511 |
5 |
liubenoff |
|
512 |
|
|
|
513 |
|
|
Path information for path number 5:
|
514 |
6 |
liubenoff |
Requested Period: 2.255
|
515 |
5 |
liubenoff |
- Setup time: 0.211
|
516 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
517 |
6 |
liubenoff |
= Required time: 2.044
|
518 |
5 |
liubenoff |
|
519 |
6 |
liubenoff |
- Propagation time: 2.382
|
520 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
521 |
6 |
liubenoff |
= Slack (non-critical) : -0.339
|
522 |
5 |
liubenoff |
|
523 |
6 |
liubenoff |
Number of logic level(s): 3
|
524 |
|
|
Starting point: symbol_scan_cntr[1] / Q
|
525 |
|
|
Ending point: symbol_scan_cntr[5] / D
|
526 |
|
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
527 |
|
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
528 |
5 |
liubenoff |
|
529 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
530 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
531 |
|
|
-------------------------------------------------------------------------------------------
|
532 |
|
|
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
|
533 |
|
|
symbol_scan_cntr[1] Net - - - - 15
|
534 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
535 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
536 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
537 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
538 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
539 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
540 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
541 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
|
542 |
|
|
symbol_scan_cntr_s[5] Net - - - - 1
|
543 |
|
|
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
|
544 |
|
|
===========================================================================================
|
545 |
5 |
liubenoff |
|
546 |
|
|
|
547 |
|
|
|
548 |
|
|
##### END OF TIMING REPORT #####]
|
549 |
|
|
|
550 |
|
|
Constraints that could not be applied
|
551 |
|
|
None
|
552 |
|
|
|
553 |
6 |
liubenoff |
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
554 |
5 |
liubenoff |
|
555 |
|
|
|
556 |
6 |
liubenoff |
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
557 |
5 |
liubenoff |
|
558 |
|
|
---------------------------------------
|
559 |
|
|
Resource Usage Report
|
560 |
|
|
Part: lfe5um5g_45f-8
|
561 |
|
|
|
562 |
6 |
liubenoff |
Register bits: 9 of 43848 (0%)
|
563 |
5 |
liubenoff |
PIC Latch: 0
|
564 |
|
|
I/O cells: 18
|
565 |
|
|
|
566 |
|
|
|
567 |
|
|
Details:
|
568 |
6 |
liubenoff |
CCU2C: 5
|
569 |
|
|
FD1S3DX: 9
|
570 |
5 |
liubenoff |
GSR: 1
|
571 |
|
|
IB: 2
|
572 |
6 |
liubenoff |
INV: 1
|
573 |
5 |
liubenoff |
OB: 16
|
574 |
|
|
PUR: 1
|
575 |
6 |
liubenoff |
ROM128X1A: 14
|
576 |
|
|
VHI: 1
|
577 |
5 |
liubenoff |
VLO: 1
|
578 |
|
|
Mapper successful!
|
579 |
|
|
|
580 |
6 |
liubenoff |
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
581 |
5 |
liubenoff |
|
582 |
6 |
liubenoff |
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
583 |
|
|
# Tue Jan 17 01:19:13 2017
|
584 |
5 |
liubenoff |
|
585 |
|
|
###########################################################]
|