URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.tw1] - Blame information for rev 9

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Loading design for application trce from file displaydriverwdecoder_impl1_map.ncd.
Design name: display_driver_wrapper
NCD version: 3.3
Vendor:      LATTICE
Device:      LFE5UM5G-45F
Package:     CABGA381
Performance: 8
Loading device for application trce from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
Package Status:                     Final          Version 1.36.
Performance Hardware Data Status:   Final          Version 50.1.
Setup and Hold Report
 
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.8.0.115.3
Wed Jan 18 01:08:27 2017
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
 
Report Information
------------------
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf
Design file:     displaydriverwdecoder_impl1_map.ncd
Preference file: displaydriverwdecoder_impl1.prf
Device,speed:    LFE5UM5G-45F,8
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
 
Report Type:     based on TRACE automatically generated preferences
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
 
 
 
================================================================================
Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;
            68 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 
 
Passed:  The following path meets requirements by 0.001ns
         The internal maximum frequency of the following component is 370.096 MHz
 
 Logical Details:  Cell type  Pin name       Component name
 
   Destination:    SIOLOGIC   CLK            button_MGIOL
 
   Delay:               2.702ns -- based on Minimum Pulse Width
 
 
Passed: The following path meets requirements by 1.063ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
   Source:         FF         Q              bttn_state  (from clk_c +)
   Destination:    FF         Data in        symbol_scan_cntr[7]  (to clk_c +)
 
   Delay:               1.749ns  (43.2% logic, 56.8% route), 3 logic levels.
 
 Constraint Details:
 
      1.749ns physical path delay SLICE_7 to SLICE_0 meets
      2.703ns delay constraint less
     -0.109ns CE_SET requirement (totaling 2.812ns) by 1.063ns
 
 Physical Path Details:
 
      Data path SLICE_7 to SLICE_0:
 
   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.395    SLICE_7.CLK to     SLICE_7.Q0 SLICE_7 (from clk_c)
ROUTE         1   e 0.419     SLICE_7.Q0 to    SLICE_64.B1 bttn_state_i
CTOF_DEL    ---     0.180    SLICE_64.B1 to    SLICE_64.F1 SLICE_64
ROUTE         1   e 0.156    SLICE_64.F1 to    SLICE_64.A0 G_15_1
CTOF_DEL    ---     0.180    SLICE_64.A0 to    SLICE_64.F0 SLICE_64
ROUTE         5   e 0.419    SLICE_64.F0 to     SLICE_0.CE bttn_state_fifo_0io_RNIB9K02[0] (to clk_c)
                  --------
                    1.749   (43.2% logic, 56.8% route), 3 logic levels.
 
Report:  370.096MHz is the maximum frequency for this preference.
 
Report Summary
--------------
----------------------------------------------------------------------------
Preference                              |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "clk_c" 369.959000 MHz ;  |  369.959 MHz|  370.096 MHz|   0
                                        |             |             |
----------------------------------------------------------------------------
 
 
All preferences were met.
 
 
Clock Domains Analysis
------------------------
 
Found 1 clocks:
 
Clock Domain: clk_c   Source: clk.PAD   Loads: 9
   Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;
 
 
Timing summary (Setup):
---------------
 
Timing errors: 0  Score: 0
Cumulative negative slack: 0
 
Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)
 
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.8.0.115.3
Wed Jan 18 01:08:28 2017
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
 
Report Information
------------------
Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf
Design file:     displaydriverwdecoder_impl1_map.ncd
Preference file: displaydriverwdecoder_impl1.prf
Device,speed:    LFE5UM5G-45F,M
Report level:    verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
 
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
 
 
 
================================================================================
Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;
            68 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
 
 
Passed: The following path meets requirements by 0.104ns
 
 Logical Details:  Cell type  Pin type       Cell/ASIC name  (clock net +/-)
 
   Source:         FF         Q              bttn_state_fifo[1]  (from clk_c +)
   Destination:    FF         Data in        bttn_state_fifo[2]  (to clk_c +)
 
   Delay:               0.222ns  (73.9% logic, 26.1% route), 1 logic levels.
 
 Constraint Details:
 
      0.222ns physical path delay SLICE_5 to SLICE_5 meets
      0.118ns M_HLD and
      0.000ns delay constraint requirement (totaling 0.118ns) by 0.104ns
 
 Physical Path Details:
 
      Data path SLICE_5 to SLICE_5:
 
   Name    Fanout   Delay (ns)          Site               Resource
REG_DEL     ---     0.164    SLICE_5.CLK to     SLICE_5.Q0 SLICE_5 (from clk_c)
ROUTE         3   e 0.058     SLICE_5.Q0 to     SLICE_5.M1 bttn_state_fifo[1] (to clk_c)
                  --------
                    0.222   (73.9% logic, 26.1% route), 1 logic levels.
 
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays)                  |   Constraint|       Actual|Levels
----------------------------------------------------------------------------
                                        |             |             |
FREQUENCY NET "clk_c" 369.959000 MHz ;  |     0.000 ns|     0.104 ns|   1
                                        |             |             |
----------------------------------------------------------------------------
 
 
All preferences were met.
 
 
Clock Domains Analysis
------------------------
 
Found 1 clocks:
 
Clock Domain: clk_c   Source: clk.PAD   Loads: 9
   Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;
 
 
Timing summary (Hold):
---------------
 
Timing errors: 0  Score: 0
Cumulative negative slack: 0
 
Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)
 
 
 
Timing summary (Setup and Hold):
---------------
 
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
 
--------------------------------------------------------------------------------
 

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1.tw1] - Blame information for rev 9

Line No.	Rev	Author	Line
1	5	liubenoff
2			`Loading design for application trce from file displaydriverwdecoder_impl1_map.ncd.`
3	9	liubenoff	`Design name: display_driver_wrapper`
4	5	liubenoff	`NCD version: 3.3`
5			`Vendor: LATTICE`
6			`Device: LFE5UM5G-45F`
7			`Package: CABGA381`
8			`Performance: 8`
9			`Loading device for application trce from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.`
10			`Package Status: Final Version 1.36.`
11			`Performance Hardware Data Status: Final Version 50.1.`
12			`Setup and Hold Report`
13
14			`--------------------------------------------------------------------------------`
15			`Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.8.0.115.3`
16	9	liubenoff	`Wed Jan 18 01:08:27 2017`
17	5	liubenoff
18			`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
19			`Copyright (c) 1995 AT&T Corp. All rights reserved.`
20			`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
21			`Copyright (c) 2001 Agere Systems All rights reserved.`
22			`Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.`
23
24			`Report Information`
25			`------------------`
26			`Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf`
27			`Design file: displaydriverwdecoder_impl1_map.ncd`
28			`Preference file: displaydriverwdecoder_impl1.prf`
29			`Device,speed: LFE5UM5G-45F,8`
30			`Report level: verbose report, limited to 1 item per preference`
31			`--------------------------------------------------------------------------------`
32
33	6	liubenoff	`Report Type: based on TRACE automatically generated preferences`
34	5	liubenoff	`BLOCK ASYNCPATHS`
35			`BLOCK RESETPATHS`
36			`--------------------------------------------------------------------------------`
37
38
39
40			`================================================================================`
41	6	liubenoff	`Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;`
42			`68 items scored, 0 timing errors detected.`
43	5	liubenoff	`--------------------------------------------------------------------------------`
44
45
46	6	liubenoff	`Passed: The following path meets requirements by 0.001ns`
47			`The internal maximum frequency of the following component is 370.096 MHz`
48	5	liubenoff
49	6	liubenoff	`Logical Details: Cell type Pin name Component name`
50
51			`Destination: SIOLOGIC CLK button_MGIOL`
52
53			`Delay: 2.702ns -- based on Minimum Pulse Width`
54
55
56			`Passed: The following path meets requirements by 1.063ns`
57
58			`Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)`
59
60			`Source: FF Q bttn_state (from clk_c +)`
61			`Destination: FF Data in symbol_scan_cntr[7] (to clk_c +)`
62
63			`Delay: 1.749ns (43.2% logic, 56.8% route), 3 logic levels.`
64
65			`Constraint Details:`
66
67			`1.749ns physical path delay SLICE_7 to SLICE_0 meets`
68			`2.703ns delay constraint less`
69			`-0.109ns CE_SET requirement (totaling 2.812ns) by 1.063ns`
70
71			`Physical Path Details:`
72
73			`Data path SLICE_7 to SLICE_0:`
74
75			`Name Fanout Delay (ns) Site Resource`
76			`REG_DEL --- 0.395 SLICE_7.CLK to SLICE_7.Q0 SLICE_7 (from clk_c)`
77			`ROUTE 1 e 0.419 SLICE_7.Q0 to SLICE_64.B1 bttn_state_i`
78			`CTOF_DEL --- 0.180 SLICE_64.B1 to SLICE_64.F1 SLICE_64`
79			`ROUTE 1 e 0.156 SLICE_64.F1 to SLICE_64.A0 G_15_1`
80			`CTOF_DEL --- 0.180 SLICE_64.A0 to SLICE_64.F0 SLICE_64`
81			`ROUTE 5 e 0.419 SLICE_64.F0 to SLICE_0.CE bttn_state_fifo_0io_RNIB9K02[0] (to clk_c)`
82			`--------`
83			`1.749 (43.2% logic, 56.8% route), 3 logic levels.`
84
85			`Report: 370.096MHz is the maximum frequency for this preference.`
86
87	5	liubenoff	`Report Summary`
88			`--------------`
89			`----------------------------------------------------------------------------`
90			`Preference \| Constraint\| Actual\|Levels`
91			`----------------------------------------------------------------------------`
92			`\| \| \|`
93	6	liubenoff	`FREQUENCY NET "clk_c" 369.959000 MHz ; \| 369.959 MHz\| 370.096 MHz\| 0`
94	5	liubenoff	`\| \| \|`
95			`----------------------------------------------------------------------------`
96
97
98			`All preferences were met.`
99
100
101			`Clock Domains Analysis`
102			`------------------------`
103
104	6	liubenoff	`Found 1 clocks:`
105	5	liubenoff
106	6	liubenoff	`Clock Domain: clk_c Source: clk.PAD Loads: 9`
107			`Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;`
108	5	liubenoff
109	6	liubenoff
110	5	liubenoff	`Timing summary (Setup):`
111			`---------------`
112
113			`Timing errors: 0 Score: 0`
114			`Cumulative negative slack: 0`
115
116	6	liubenoff	`Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)`
117	5	liubenoff
118			`--------------------------------------------------------------------------------`
119	6	liubenoff	`Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.8.0.115.3`
120	9	liubenoff	`Wed Jan 18 01:08:28 2017`
121	5	liubenoff
122	6	liubenoff	`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
123			`Copyright (c) 1995 AT&T Corp. All rights reserved.`
124			`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
125			`Copyright (c) 2001 Agere Systems All rights reserved.`
126			`Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.`
127
128			`Report Information`
129			`------------------`
130			`Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf`
131			`Design file: displaydriverwdecoder_impl1_map.ncd`
132			`Preference file: displaydriverwdecoder_impl1.prf`
133			`Device,speed: LFE5UM5G-45F,M`
134			`Report level: verbose report, limited to 1 item per preference`
135			`--------------------------------------------------------------------------------`
136
137			`BLOCK ASYNCPATHS`
138			`BLOCK RESETPATHS`
139			`--------------------------------------------------------------------------------`
140
141
142
143			`================================================================================`
144			`Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;`
145			`68 items scored, 0 timing errors detected.`
146			`--------------------------------------------------------------------------------`
147
148
149			`Passed: The following path meets requirements by 0.104ns`
150
151			`Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)`
152
153			`Source: FF Q bttn_state_fifo[1] (from clk_c +)`
154			`Destination: FF Data in bttn_state_fifo[2] (to clk_c +)`
155
156			`Delay: 0.222ns (73.9% logic, 26.1% route), 1 logic levels.`
157
158			`Constraint Details:`
159
160			`0.222ns physical path delay SLICE_5 to SLICE_5 meets`
161			`0.118ns M_HLD and`
162			`0.000ns delay constraint requirement (totaling 0.118ns) by 0.104ns`
163
164			`Physical Path Details:`
165
166			`Data path SLICE_5 to SLICE_5:`
167
168			`Name Fanout Delay (ns) Site Resource`
169			`REG_DEL --- 0.164 SLICE_5.CLK to SLICE_5.Q0 SLICE_5 (from clk_c)`
170			`ROUTE 3 e 0.058 SLICE_5.Q0 to SLICE_5.M1 bttn_state_fifo[1] (to clk_c)`
171			`--------`
172			`0.222 (73.9% logic, 26.1% route), 1 logic levels.`
173
174			`Report Summary`
175			`--------------`
176			`----------------------------------------------------------------------------`
177			`Preference(MIN Delays) \| Constraint\| Actual\|Levels`
178			`----------------------------------------------------------------------------`
179			`\| \| \|`
180			`FREQUENCY NET "clk_c" 369.959000 MHz ; \| 0.000 ns\| 0.104 ns\| 1`
181			`\| \| \|`
182			`----------------------------------------------------------------------------`
183
184
185			`All preferences were met.`
186
187
188			`Clock Domains Analysis`
189			`------------------------`
190
191			`Found 1 clocks:`
192
193			`Clock Domain: clk_c Source: clk.PAD Loads: 9`
194			`Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;`
195
196
197			`Timing summary (Hold):`
198			`---------------`
199
200			`Timing errors: 0 Score: 0`
201			`Cumulative negative slack: 0`
202
203			`Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)`
204
205
206
207			`Timing summary (Setup and Hold):`
208			`---------------`
209
210			`Timing errors: 0 (setup), 0 (hold)`
211			`Score: 0 (setup), 0 (hold)`
212			`Cumulative negative slack: 0 (0+0)`
213			`--------------------------------------------------------------------------------`
214
215			`--------------------------------------------------------------------------------`
216