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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_cck.rpt] - Blame information for rev 9

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# Synopsys Constraint Checker, version maplat, Build 1498R, built Jul  5 2016
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# Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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# Written on Wed Jan 18 01:08:15 2017
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##### DESIGN INFO #######################################################
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Top View:                "display_driver_wrapper"
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Constraint File(s):      (none)
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##### SUMMARY ############################################################
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Found 0 issues in 0 out of 0 constraints
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##### DETAILS ############################################################
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Clock Relationships
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*******************
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Starting                                            Ending                                              |     rise to rise     |     fall to fall     |     rise to fall     |     fall to rise
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-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
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display_driver_wrapper|clk                          display_driver_wrapper|clk                          |     1000.000         |     No paths         |     No paths         |     No paths
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display_driver_wrapper|bttn_state_derived_clock     display_driver_wrapper|bttn_state_derived_clock     |     1000.000         |     No paths         |     No paths         |     No paths
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===================================================================================================================================================================================================================
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 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
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       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
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Unconstrained Start/End Points
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******************************
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p:button
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p:disp_data_q[0]
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p:disp_data_q[1]
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p:disp_data_q[2]
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p:disp_data_q[3]
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p:disp_data_q[4]
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p:disp_data_q[5]
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p:disp_data_q[6]
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p:disp_data_q[7]
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p:disp_data_q[8]
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p:disp_data_q[9]
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p:disp_data_q[10]
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p:disp_data_q[11]
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p:disp_data_q[12]
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p:disp_data_q[13]
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p:disp_data_q[14]
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p:n_rst
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Inapplicable constraints
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************************
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(none)
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Applicable constraints with issues
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**********************************
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(none)
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Constraints with matching wildcard expressions
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**********************************************
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(none)
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Library Report
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**************
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# End of Constraint Checker Report

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