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<HEAD><TITLE>Project Summary</TITLE>
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</HEAD>
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<PRE><A name="Mrp"></A>
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Lattice Mapping Report File for Design Module 'DisplayDriverWrapper'
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<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
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Command line: map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial
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DisplayDriverwDecoder_impl1.ngd -o DisplayDriverwDecoder_impl1_map.ncd -pr
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DisplayDriverwDecoder_impl1.prf -mp DisplayDriverwDecoder_impl1.mrp -lpf C:
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/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_B
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uild/impl1/DisplayDriverwDecoder_impl1_synplify.lpf -lpf C:/Projects/single
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-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriv
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erwDecoder.lpf -gui -msgset C:/Projects/single-14-segment-display-driver-w-
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decoder/Project/Lattice_FPGA_Build/promote.xml
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Target Vendor: LATTICE
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Target Device: LFE5UM5G-45FCABGA381
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Target Performance: 8
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Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3
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Mapped on: 01/17/17 01:36:37
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<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
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Number of registers: 13 out of 44457 (0%)
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PFU registers: 12 out of 43848 (0%)
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PIO registers: 1 out of 609 (0%)
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Number of SLICEs: 65 out of 21924 (0%)
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SLICEs as Logic/ROM: 65 out of 21924 (0%)
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SLICEs as RAM: 0 out of 16443 (0%)
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SLICEs as Carry: 5 out of 21924 (0%)
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Number of LUT4s: 127 out of 43848 (0%)
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Number used as logic LUTs: 117
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Number used as distributed RAM: 0
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Number used as ripple logic: 10
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Number used as shift registers: 0
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Number of PIO sites used: 20 out of 203 (10%)
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Number of PIO sites used for single ended IOs: 18
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Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
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comps in NCD)
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Number of block RAMs: 0 out of 108 (0%)
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Number of GSRs: 1 out of 1 (100%)
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JTAG used : No
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Readback used : No
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Oscillator used : No
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Startup used : No
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DTR used : No
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Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)
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Number of Dynamic Bank Controller (BCLVDSOB): 0 out of 4 (0%)
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Number of DCC: 0 out of 60 (0%)
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Number of DCS: 0 out of 2 (0%)
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Number of PLLs: 0 out of 4 (0%)
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Number of DDRDLLs: 0 out of 4 (0%)
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Number of CLKDIV: 0 out of 4 (0%)
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Number of ECLKSYNC: 0 out of 10 (0%)
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Number of ECLKBRIDGECS: 0 out of 2 (0%)
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Number of DCUs: 0 out of 2 (0%)
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Number of DCU Channels: 0 out of 4 (0%)
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Number of EXTREFs: 0 out of 2 (0%)
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1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
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distributed RAMs) + 2*(Number of ripple logic)
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ripple logic.
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Number Of Mapped DSP Components:
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--------------------------------
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MULT18X18D 0
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MULT9X9D 0
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ALU54B 0
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ALU24B 0
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PRADD18A 0
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PRADD9A 0
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--------------------------------
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Number of Used DSP MULT Sites: 0 out of 144 (0 %)
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Number of Used DSP ALU Sites: 0 out of 72 (0 %)
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Number of Used DSP PRADD Sites: 0 out of 144 (0 %)
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Number of clocks: 1
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Net clk_c: 9 loads, 9 rising, 0 falling (Driver: PIO clk )
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Number of Clock Enables: 1
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Number of local set/reset loads for net n_rst_c merged into GSR: 8
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Number of LSRs: 1
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Net n_rst_c: 3 loads, 2 LSLICEs
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Number of nets driven by tri-state buffers: 0
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Top 10 highest fanout non-clock nets:
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Net symbol_scan_cntr[5]: 86 loads
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Net symbol_scan_cntr[4]: 29 loads
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Net symbol_scan_cntr[0]: 15 loads
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Net n_rst_c: 6 loads
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Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads
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Net bttn_state_fifo[0]: 3 loads
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Number of warnings: 4
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Number of errors: 0
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<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
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WARNING - map: C:/Projects/single-14-segment-display-driver-w-decoder/Project/La
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ttice_FPGA_Build/DisplayDriverwDecoder.lpf(21): Semantic error in "USERCODE
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ASCII "G.L." ; ": Invalid Ascii char <.>.Invalid Ascii char <.>.. This
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preference has been disabled.
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WARNING - map: Preference parsing results: 1 semantic error detected.
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WARNING - map: Using local reset signal 'n_rst_c' to infer global GSR net.
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WARNING - map: There are semantic errors in the preference file C:/Projects/sing
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le-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDr
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iverwDecoder.lpf.
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<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
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+---------------------+-----------+-----------+------------+
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| IO Name | Direction | Levelmode | IO |
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| | | IO_TYPE | Register |
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+---------------------+-----------+-----------+------------+
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| disp_data[0] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| clk | INPUT | LVDS | |
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+---------------------+-----------+-----------+------------+
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| disp_sel | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[14] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[13] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[12] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[11] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[10] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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+---------------------+-----------+-----------+------------+
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| disp_data[8] | OUTPUT | LVCMOS25 | |
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| disp_data[7] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[6] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[5] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[4] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[3] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[2] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| disp_data[1] | OUTPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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| button | INPUT | LVCMOS25 | IN |
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+---------------------+-----------+-----------+------------+
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| n_rst | INPUT | LVCMOS25 | |
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+---------------------+-----------+-----------+------------+
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<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
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Signal n_rst_c_i was merged into signal n_rst_c
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Signal GND undriven or does not drive anything - clipped.
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Signal VCC undriven or does not drive anything - clipped.
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Signal symbol_scan_cntr_cry_0_S0[0] undriven or does not drive anything -
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clipped.
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Signal N_1 undriven or does not drive anything - clipped.
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Signal symbol_scan_cntr_s_0_S1[7] undriven or does not drive anything - clipped.
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Block GND was optimized away.
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Block VCC was optimized away.
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<A name="mrp_gsr"></A><B><U><big>GSR Usage</big></U></B>
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---------
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GSR Component:
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The local reset signal 'n_rst_c' of the design has been inferred as Global
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Set Reset (GSR). The reset signal used for GSR control is 'n_rst_c'.
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not.
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Components on inferred reset domain with GSR Property disabled
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--------------------------------------------------------------
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These components have the GSR property set to DISABLED and are on the
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inferred reset domain. The components will respond to the reset signal
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'n_rst_c' via the local reset on the component and not the GSR component.
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Type and number of components of the type:
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Register = 4
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Type and instance name of component:
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Register : bttn_state_fifo[3]
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Register : bttn_state_fifo_0io[0]
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Register : bttn_state_fifo[1]
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Register : bttn_state_fifo[2]
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<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
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-------------------------
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Total CPU Time: 1 secs
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Total REAL Time: 2 secs
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Peak Memory Usage: 152 MB
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights
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