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[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_mrp.html] - Blame information for rev 9

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<PRE><A name="Mrp"></A>
    Lattice Mapping Report File for Design Module 'display_driver_wrapper'
 
 
 
<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>
 
Command line:   map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial
     DisplayDriverwDecoder_impl1.ngd -o DisplayDriverwDecoder_impl1_map.ncd -pr
     DisplayDriverwDecoder_impl1.prf -mp DisplayDriverwDecoder_impl1.mrp -lpf C:
     /Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_B
     uild/impl1/DisplayDriverwDecoder_impl1_synplify.lpf -lpf C:/Projects/single
     -14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriv
     erwDecoder.lpf -gui -msgset C:/Projects/single-14-segment-display-driver-w-
     decoder/Project/Lattice_FPGA_Build/promote.xml
Target Vendor:  LATTICE
Target Device:  LFE5UM5G-45FCABGA381
Target Performance:   8
Mapper:  sa5p00g,  version:  Diamond (64-bit) 3.8.0.115.3
Mapped on:  01/18/17  01:08:21
 
 
<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>
   Number of registers:     13 out of 44457 (0%)
      PFU registers:           12 out of 43848 (0%)
      PIO registers:            1 out of   609 (0%)
   Number of SLICEs:        65 out of 21924 (0%)
      SLICEs as Logic/ROM:     65 out of 21924 (0%)
      SLICEs as RAM:            0 out of 16443 (0%)
      SLICEs as Carry:          5 out of 21924 (0%)
   Number of LUT4s:        127 out of 43848 (0%)
      Number used as logic LUTs:        117
      Number used as distributed RAM:     0
      Number used as ripple logic:       10
      Number used as shift registers:     0
   Number of PIO sites used: 19 out of 203 (9%)
      Number of PIO sites used for single ended IOs: 17
      Number of PIO sites used for differential IOs: 2 (represented by 1 PIO
     comps in NCD)
   Number of block RAMs:  0 out of 108 (0%)
   Number of GSRs:  1 out of 1 (100%)
   JTAG used :      No
   Readback used :  No
   Oscillator used :  No
   Startup used :   No
   DTR used :   No
   Number of Dynamic Bank Controller (BCINRD):  0 out of 4 (0%)
   Number of Dynamic Bank Controller (BCLVDSOB):  0 out of 4 (0%)
   Number of DCC:  0 out of 60 (0%)
   Number of DCS:  0 out of 2 (0%)
   Number of PLLs:  0 out of 4 (0%)
   Number of DDRDLLs:  0 out of 4 (0%)
   Number of CLKDIV:  0 out of 4 (0%)
   Number of ECLKSYNC:  0 out of 10 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Number of DCUs:  0 out of 2 (0%)
   Number of DCU Channels:  0 out of 4 (0%)
   Number of EXTREFs:  0 out of 2 (0%)
 
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
 
 
     ripple logic.
 
        Number Of Mapped DSP Components:
   --------------------------------
   MULT18X18D          0
   MULT9X9D            0
   ALU54B              0
   ALU24B              0
   PRADD18A            0
   PRADD9A             0
   --------------------------------
   Number of Used DSP MULT Sites:  0 out of 144 (0 %)
   Number of Used DSP ALU Sites:  0 out of 72 (0 %)
   Number of Used DSP PRADD Sites:  0 out of 144 (0 %)
   Number of clocks:  1
     Net clk_c: 9 loads, 9 rising, 0 falling (Driver: PIO clk )
   Number of Clock Enables:  1
 
   Number of local set/reset loads for net n_rst_c merged into GSR:  8
   Number of LSRs:  1
     Net n_rst_c: 3 loads, 2 LSLICEs
   Number of nets driven by tri-state buffers:  0
   Top 10 highest fanout non-clock nets:
 
 
 
     Net symbol_scan_cntr[5]: 86 loads
 
     Net symbol_scan_cntr[4]: 29 loads
     Net symbol_scan_cntr[0]: 15 loads
     Net n_rst_c: 6 loads
     Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads
     Net bttn_state_fifo[0]: 3 loads
 
 
 
 
   Number of warnings:  4
   Number of errors:    0
 
 
 
 
 
<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>
 
WARNING - map: C:/Projects/single-14-segment-display-driver-w-decoder/Project/La
     ttice_FPGA_Build/DisplayDriverwDecoder.lpf(29): Semantic error in "USERCODE
     ASCII "G.L." ; ": Invalid Ascii char <.>.Invalid Ascii char <.>.. This
     preference has been disabled.
WARNING - map: Preference parsing results:  1 semantic error detected.
WARNING - map: Using local reset signal 'n_rst_c' to infer global GSR net.
WARNING - map: There are semantic errors in the preference file C:/Projects/sing
     le-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDr
     iverwDecoder.lpf.
 
 
 
 
 
<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>
 
+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| disp_data_q[0]      | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| clk                 | INPUT     | LVDS      |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[14]     | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[13]     | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[12]     | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[11]     | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[10]     | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[9]      | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
 
+---------------------+-----------+-----------+------------+
| disp_data_q[7]      | OUTPUT    | LVCMOS25  |            |
 
| disp_data_q[6]      | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[5]      | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[4]      | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[3]      | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[2]      | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| disp_data_q[1]      | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| button              | INPUT     | LVCMOS25  | IN         |
+---------------------+-----------+-----------+------------+
| n_rst               | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
 
 
 
<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>
 
Block GND undriven or does not drive anything - clipped.
Signal n_rst_c_i was merged into signal n_rst_c
Signal VCC undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_cry_0_S0[0] undriven or does not drive anything -
     clipped.
Signal N_1 undriven or does not drive anything - clipped.
Signal symbol_scan_cntr_s_0_S1[7] undriven or does not drive anything - clipped.
 
Signal symbol_scan_cntr_s_0_COUT[7] undriven or does not drive anything -
     clipped.
 
 
 
 
 
 
 
 
 
 
 
 
 
<A name="mrp_gsr"></A><B><U><big>GSR Usage</big></U></B>
---------
 
GSR Component:
   The local reset signal 'n_rst_c' of the design has been inferred as Global
        Set Reset (GSR). The reset signal used for GSR control is 'n_rst_c'.
 
 
     GSR Property:
 
 
 
 
 
     Components on inferred reset domain with GSR Property disabled
 
 
     These components have the GSR property set to DISABLED and are on the
     inferred reset domain. The components will respond to the reset signal
     'n_rst_c' via the local reset on the component and not the GSR component.
 
     Type and number of components of the type:
   Register = 4
 
     Type and instance name of component:
   Register : bttn_state_fifo[3]
   Register : bttn_state_fifo_0io[0]
   Register : bttn_state_fifo[1]
   Register : bttn_state_fifo[2]
 
 
 
<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>
-------------------------
 
   Total CPU Time: 1 secs
   Total REAL Time: 3 secs
   Peak Memory Usage: 152 MB
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
     Copyright (c) 1995 AT&T Corp.   All rights reserved.
     Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
 
 
 
 
 
 
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Line No.	Rev	Author	Line
1	5	liubenoff	`<HTML>`
2			`<HEAD><TITLE>Project Summary</TITLE>`
3			`<STYLE TYPE="text/css">`
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8			`</HEAD>`
9			`<PRE><A name="Mrp"></A>`
10			`Lattice Mapping Report File for Design Module 'display_driver_wrapper'`
11
12
13
14			`<A name="mrp_di"></A><B><U><big>Design Information</big></U></B>`
15
16			`Command line: map -a ECP5UM5G -p LFE5UM5G-45F -t CABGA381 -s 8 -oc Commercial`
17			`DisplayDriverwDecoder_impl1.ngd -o DisplayDriverwDecoder_impl1_map.ncd -pr`
18			`DisplayDriverwDecoder_impl1.prf -mp DisplayDriverwDecoder_impl1.mrp -lpf C:`
19			`/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_B`
20			`uild/impl1/DisplayDriverwDecoder_impl1_synplify.lpf -lpf C:/Projects/single`
21			`-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriv`
22			`erwDecoder.lpf -gui -msgset C:/Projects/single-14-segment-display-driver-w-`
23			`decoder/Project/Lattice_FPGA_Build/promote.xml`
24			`Target Vendor: LATTICE`
25			`Target Device: LFE5UM5G-45FCABGA381`
26			`Target Performance: 8`
27			`Mapper: sa5p00g, version: Diamond (64-bit) 3.8.0.115.3`
28			`Mapped on: 01/18/17 01:08:21`
29
30
31			`<A name="mrp_ds"></A><B><U><big>Design Summary</big></U></B>`
32			`Number of registers: 13 out of 44457 (0%)`
33			`PFU registers: 12 out of 43848 (0%)`
34			`PIO registers: 1 out of 609 (0%)`
35			`Number of SLICEs: 65 out of 21924 (0%)`
36			`SLICEs as Logic/ROM: 65 out of 21924 (0%)`
37			`SLICEs as RAM: 0 out of 16443 (0%)`
38			`SLICEs as Carry: 5 out of 21924 (0%)`
39			`Number of LUT4s: 127 out of 43848 (0%)`
40			`Number used as logic LUTs: 117`
41			`Number used as distributed RAM: 0`
42			`Number used as ripple logic: 10`
43			`Number used as shift registers: 0`
44			`Number of PIO sites used: 19 out of 203 (9%)`
45			`Number of PIO sites used for single ended IOs: 17`
46			`Number of PIO sites used for differential IOs: 2 (represented by 1 PIO`
47			`comps in NCD)`
48			`Number of block RAMs: 0 out of 108 (0%)`
49			`Number of GSRs: 1 out of 1 (100%)`
50			`JTAG used : No`
51			`Readback used : No`
52			`Oscillator used : No`
53			`Startup used : No`
54			`DTR used : No`
55			`Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%)`
56			`Number of Dynamic Bank Controller (BCLVDSOB): 0 out of 4 (0%)`
57			`Number of DCC: 0 out of 60 (0%)`
58			`Number of DCS: 0 out of 2 (0%)`
59			`Number of PLLs: 0 out of 4 (0%)`
60			`Number of DDRDLLs: 0 out of 4 (0%)`
61			`Number of CLKDIV: 0 out of 4 (0%)`
62			`Number of ECLKSYNC: 0 out of 10 (0%)`
63			`Number of ECLKBRIDGECS: 0 out of 2 (0%)`
64			`Number of DCUs: 0 out of 2 (0%)`
65			`Number of DCU Channels: 0 out of 4 (0%)`
66			`Number of EXTREFs: 0 out of 2 (0%)`
67
68			`1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of`
69			`distributed RAMs) + 2*(Number of ripple logic)`
70
71
72			`ripple logic.`
73
74			`Number Of Mapped DSP Components:`
75			`--------------------------------`
76			`MULT18X18D 0`
77			`MULT9X9D 0`
78			`ALU54B 0`
79			`ALU24B 0`
80			`PRADD18A 0`
81			`PRADD9A 0`
82			`--------------------------------`
83			`Number of Used DSP MULT Sites: 0 out of 144 (0 %)`
84			`Number of Used DSP ALU Sites: 0 out of 72 (0 %)`
85			`Number of Used DSP PRADD Sites: 0 out of 144 (0 %)`
86			`Number of clocks: 1`
87			`Net clk_c: 9 loads, 9 rising, 0 falling (Driver: PIO clk )`
88			`Number of Clock Enables: 1`
89
90			`Number of local set/reset loads for net n_rst_c merged into GSR: 8`
91			`Number of LSRs: 1`
92			`Net n_rst_c: 3 loads, 2 LSLICEs`
93			`Number of nets driven by tri-state buffers: 0`
94	9	liubenoff	`Top 10 highest fanout non-clock nets:`
95	5	liubenoff
96
97
98			`Net symbol_scan_cntr[5]: 86 loads`
99
100			`Net symbol_scan_cntr[4]: 29 loads`
101			`Net symbol_scan_cntr[0]: 15 loads`
102			`Net n_rst_c: 6 loads`
103			`Net bttn_state_fifo_0io_RNIB9K02[0]: 5 loads`
104			`Net bttn_state_fifo[0]: 3 loads`
105
106
107
108
109			`Number of warnings: 4`
110			`Number of errors: 0`
111
112	9	liubenoff
113	5	liubenoff
114
115
116	6	liubenoff	`<A name="mrp_dwe"></A><B><U><big>Design Errors/Warnings</big></U></B>`
117
118			`WARNING - map: C:/Projects/single-14-segment-display-driver-w-decoder/Project/La`
119			`ttice_FPGA_Build/DisplayDriverwDecoder.lpf(29): Semantic error in "USERCODE`
120			`ASCII "G.L." ; ": Invalid Ascii char <.>.Invalid Ascii char <.>.. This`
121	5	liubenoff	`preference has been disabled.`
122	6	liubenoff	`WARNING - map: Preference parsing results: 1 semantic error detected.`
123			`WARNING - map: Using local reset signal 'n_rst_c' to infer global GSR net.`
124			`WARNING - map: There are semantic errors in the preference file C:/Projects/sing`
125	5	liubenoff	`le-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDr`
126	6	liubenoff	`iverwDecoder.lpf.`
127	5	liubenoff
128	9	liubenoff
129
130	6	liubenoff
131
132	5	liubenoff	`<A name="mrp_ioa"></A><B><U><big>IO (PIO) Attributes</big></U></B>`
133	6	liubenoff
134	5	liubenoff	`+---------------------+-----------+-----------+------------+`
135			`\| IO Name \| Direction \| Levelmode \| IO \|`
136			`\| \| \| IO_TYPE \| Register \|`
137			`+---------------------+-----------+-----------+------------+`
138			`\| disp_data_q[0] \| OUTPUT \| LVCMOS25 \| \|`
139			`+---------------------+-----------+-----------+------------+`
140			`\| clk \| INPUT \| LVDS \| \|`
141			`+---------------------+-----------+-----------+------------+`
142			`\| disp_data_q[14] \| OUTPUT \| LVCMOS25 \| \|`
143			`+---------------------+-----------+-----------+------------+`
144			`\| disp_data_q[13] \| OUTPUT \| LVCMOS25 \| \|`
145			`+---------------------+-----------+-----------+------------+`
146			`\| disp_data_q[12] \| OUTPUT \| LVCMOS25 \| \|`
147			`+---------------------+-----------+-----------+------------+`
148			`\| disp_data_q[11] \| OUTPUT \| LVCMOS25 \| \|`
149			`+---------------------+-----------+-----------+------------+`
150			`\| disp_data_q[10] \| OUTPUT \| LVCMOS25 \| \|`
151			`+---------------------+-----------+-----------+------------+`
152			`\| disp_data_q[9] \| OUTPUT \| LVCMOS25 \| \|`
153			`+---------------------+-----------+-----------+------------+`
154	6	liubenoff
155	5	liubenoff	`+---------------------+-----------+-----------+------------+`
156			`\| disp_data_q[7] \| OUTPUT \| LVCMOS25 \| \|`
157
158			`\| disp_data_q[6] \| OUTPUT \| LVCMOS25 \| \|`
159			`+---------------------+-----------+-----------+------------+`
160			`\| disp_data_q[5] \| OUTPUT \| LVCMOS25 \| \|`
161			`+---------------------+-----------+-----------+------------+`
162			`\| disp_data_q[4] \| OUTPUT \| LVCMOS25 \| \|`
163			`+---------------------+-----------+-----------+------------+`
164			`\| disp_data_q[3] \| OUTPUT \| LVCMOS25 \| \|`
165			`+---------------------+-----------+-----------+------------+`
166			`\| disp_data_q[2] \| OUTPUT \| LVCMOS25 \| \|`
167			`+---------------------+-----------+-----------+------------+`
168			`\| disp_data_q[1] \| OUTPUT \| LVCMOS25 \| \|`
169			`+---------------------+-----------+-----------+------------+`
170	6	liubenoff	`\| button \| INPUT \| LVCMOS25 \| IN \|`
171			`+---------------------+-----------+-----------+------------+`
172			`\| n_rst \| INPUT \| LVCMOS25 \| \|`
173			`+---------------------+-----------+-----------+------------+`
174
175
176
177	5	liubenoff	`<A name="mrp_rm"></A><B><U><big>Removed logic</big></U></B>`
178
179	6	liubenoff	`Block GND undriven or does not drive anything - clipped.`
180			`Signal n_rst_c_i was merged into signal n_rst_c`
181			`Signal VCC undriven or does not drive anything - clipped.`
182			`Signal symbol_scan_cntr_cry_0_S0[0] undriven or does not drive anything -`
183			`clipped.`
184			`Signal N_1 undriven or does not drive anything - clipped.`
185			`Signal symbol_scan_cntr_s_0_S1[7] undriven or does not drive anything - clipped.`
186
187			`Signal symbol_scan_cntr_s_0_COUT[7] undriven or does not drive anything -`
188			`clipped.`
189	5	liubenoff
190
191
192
193	6	liubenoff
194	5	liubenoff
195
196
197
198
199
200
201
202	6	liubenoff	`<A name="mrp_gsr"></A><B><U><big>GSR Usage</big></U></B>`
203	9	liubenoff	`---------`
204	6	liubenoff
205			`GSR Component:`
206			`The local reset signal 'n_rst_c' of the design has been inferred as Global`
207			`Set Reset (GSR). The reset signal used for GSR control is 'n_rst_c'.`
208
209
210			`GSR Property:`
211	5	liubenoff
212
213
214	6	liubenoff
215
216	5	liubenoff	`Components on inferred reset domain with GSR Property disabled`
217
218
219			`These components have the GSR property set to DISABLED and are on the`
220			`inferred reset domain. The components will respond to the reset signal`
221			`'n_rst_c' via the local reset on the component and not the GSR component.`
222	9	liubenoff
223	5	liubenoff	`Type and number of components of the type:`
224	6	liubenoff	`Register = 4`
225
226	9	liubenoff	`Type and instance name of component:`
227	5	liubenoff	`Register : bttn_state_fifo[3]`
228	9	liubenoff	`Register : bttn_state_fifo_0io[0]`
229	5	liubenoff	`Register : bttn_state_fifo[1]`
230	9	liubenoff	`Register : bttn_state_fifo[2]`
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234	9	liubenoff	`<A name="mrp_runtime"></A><B><U><big>Run Time and Memory Usage</big></U></B>`
235	5	liubenoff	`-------------------------`
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237	5	liubenoff	`Total CPU Time: 1 secs`
238	9	liubenoff	`Total REAL Time: 3 secs`
239	5	liubenoff	`Peak Memory Usage: 152 MB`
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255			`Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.`
256			`Copyright (c) 1995 AT&T Corp. All rights reserved.`
257			`Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.`
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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_mrp.html] - Blame information for rev 9