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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_par.html] - Blame information for rev 5

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1 5 liubenoff 
<HTML>
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<HEAD><TITLE>Place & Route Report</TITLE>
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<STYLE TYPE="text/css">
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
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Copyright (c) 2001 Agere Systems   All rights reserved.
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Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
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Fri Jan 13 00:54:53 2017
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C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
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DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
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DisplayDriverwDecoder_impl1.prf -gui -msgset
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C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml
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Preference file: DisplayDriverwDecoder_impl1.prf.
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<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
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Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
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Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
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----------   --------     -----        ------       -----------  -----------  ----         ------
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5_1   *      0            -            -            -            -            06           Complete
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* : Design saved.
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Total (real) run time for 1-seed: 6 secs
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par done!
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Lattice Place and Route Report for Design &quot;DisplayDriverwDecoder_impl1_map.ncd&quot;
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Fri Jan 13 00:54:53 2017
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<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
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PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
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Preference file: DisplayDriverwDecoder_impl1.prf.
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Placement level-cost: 5-1.
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Routing Iterations: 6
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Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.
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Design name: DisplayDriverWrapper
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NCD version: 3.3
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Vendor:      LATTICE
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Device:      LFE5UM5G-45F
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Package:     CABGA381
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Performance: 8
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Loading device for application par from file &apos;sa5p45m.nph&apos; in environment: C:/lscc/diamond/3.8_x64/ispfpga.
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Package Status:                     Final          Version 1.36.
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Performance Hardware Data Status:   Final          Version 50.1.
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License checked out.
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Ignore Preference Error(s):  True
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<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
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   PIO (prelim)      16/245           6% used
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   SLICE              0/21924         0% used
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Number of Signals: 0
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Number of Connections: 0
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Pin Constraint Summary:
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   16 out of 16 pins locked (100% locked).
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No signal is selected as Global Set/Reset.
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Starting Placer Phase 0.
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Finished Placer Phase 0.  REAL time: 5 secs
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Starting Placer Phase 1.
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Placer score = 0.
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Finished Placer Phase 1.  REAL time: 5 secs
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Starting Placer Phase 2.
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.
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Placer score =  0
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Finished Placer Phase 2.  REAL time: 5 secs
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<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
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Global Clock Resources:
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  GR_PCLK    : 0 out of 12 (0%)
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  PLL        : 0 out of 4 (0%)
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  DCS        : 0 out of 2 (0%)
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  DCC        : 0 out of 60 (0%)
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Quadrant TL Clocks:
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  PRIMARY  : 0 out of 16 (0%)
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Quadrant TR Clocks:
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  PRIMARY  : 0 out of 16 (0%)
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Edge Clocks:
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+
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   16 out of 245 (6.5%) PIO sites used.
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   16 out of 203 (7.9%) bonded PIO sites used.
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   Number of PIO comps: 16; differential: 0.
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   Number of Vref pins used: 0.
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I/O Bank Usage Summary:
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+----------+----------------+------------+------------+------------+
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| I/O Bank | Usage          | Bank Vccio | Bank Vref1 | Bank Vref2 |
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+----------+----------------+------------+------------+------------+
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| 0        | 0 / 27 (  0%)  | -          | -          | -          |
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| 1        | 0 / 33 (  0%)  | -          | -          | -          |
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| 6        | 1 / 33 (  3%)  | 2.5V       | -          | -          |
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| 8        | 1 / 13 (  7%)  | 2.5V       | -          | -          |
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Total placer CPU time: 3 secs
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Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
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Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
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All signals are completely routed.
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PAR_SUMMARY::Run status = completed
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PAR_SUMMARY::Number of unrouted conns = 0
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PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = &lt;n/a&gt;
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PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = &lt;n/a&gt;
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Total CPU  time to completion: 4 secs
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par done!
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
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