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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_par.html] - Blame information for rev 9

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<HTML>
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<HEAD><TITLE>Place & Route Report</TITLE>
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<STYLE TYPE="text/css">
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<!--
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<PRE><A name="Par"></A>PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
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Copyright (c) 2001 Agere Systems   All rights reserved.
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Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
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Wed Jan 18 01:08:29 2017
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C:/lscc/diamond/3.8_x64/ispfpga\bin\nt64\par -f DisplayDriverwDecoder_impl1.p2t
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DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir
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DisplayDriverwDecoder_impl1.prf -gui -msgset
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C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml
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Preference file: DisplayDriverwDecoder_impl1.prf.
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<A name="par_cts"></A><B><U><big>Cost Table Summary</big></U></B>
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Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
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Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
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----------   --------     -----        ------       -----------  -----------  ----         ------
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5_1   *      0            -1.238       7103         0.178        0            25           Complete
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* : Design saved.
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Total (real) run time for 1-seed: 25 secs
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par done!
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Lattice Place and Route Report for Design &quot;DisplayDriverwDecoder_impl1_map.ncd&quot;
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Wed Jan 18 01:08:29 2017
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<A name="par_best"></A><B><U><big>Best Par Run</big></U></B>
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PAR: Place And Route Diamond (64-bit) 3.8.0.115.3.
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Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml -exp parUseNBR=1:parCDP=auto:parCDR=1:parPathBased=OFF DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.dir/5_1.ncd DisplayDriverwDecoder_impl1.prf
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Preference file: DisplayDriverwDecoder_impl1.prf.
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Placement level-cost: 5-1.
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Routing Iterations: 6
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Loading design for application par from file DisplayDriverwDecoder_impl1_map.ncd.
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Design name: display_driver_wrapper
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NCD version: 3.3
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Vendor:      LATTICE
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Device:      LFE5UM5G-45F
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Package:     CABGA381
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Performance: 8
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Loading device for application par from file &apos;sa5p45m.nph&apos; in environment: C:/lscc/diamond/3.8_x64/ispfpga.
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Package Status:                     Final          Version 1.36.
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Performance Hardware Data Status:   Final          Version 50.1.
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License checked out.
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Ignore Preference Error(s):  True
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<A name="par_dus"></A><B><U><big>Device utilization summary:</big></U></B>
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   PIO (prelim)      19/245           7% used
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   IOLOGIC            1/245          &lt;1% used
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   SLICE             65/21924        &lt;1% used
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   GSR                1/1           100% used
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Number of Signals: 131
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Number of Connections: 657
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Pin Constraint Summary:
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   18 out of 18 pins locked (100% locked).
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The following 1 signal is selected to use the primary clock routing resources:
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    clk_c (driver: clk, clk/ce/sr load #: 9/0/0)
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Signal n_rst_c is selected as Global Set/Reset.
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Starting Placer Phase 0.
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.........
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Finished Placer Phase 0.  REAL time: 4 secs
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Starting Placer Phase 1.
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.......................
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Placer score = 63578.
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Finished Placer Phase 1.  REAL time: 15 secs
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Starting Placer Phase 2.
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.
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Placer score =  63553
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Finished Placer Phase 2.  REAL time: 15 secs
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<A name="par_clk"></A><B><U><big>Clock Report</big></U></B>
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Global Clock Resources:
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  PLL        : 0 out of 4 (0%)
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  DCC        : 0 out of 60 (0%)
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  CLKDIV     : 0 out of 4 (0%)
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Quadrant TL Clocks:
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Quadrant TR Clocks:
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  PRIMARY  : 0 out of 16 (0%)
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Quadrant BL Clocks:
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  PRIMARY  : 1 out of 16 (6%)
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  PRIMARY &quot;clk_c&quot; from comp &quot;clk&quot; on PIO site &quot;P3 (PL68C)&quot;, CLK/CE/SR load = 8
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  PRIMARY  : 1 out of 16 (6%)
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Edge Clocks:
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+
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I/O Usage Summary (final):
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   19 out of 245 (7.8%) PIO sites used.
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   19 out of 203 (9.4%) bonded PIO sites used.
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   Number of PIO comps: 18; differential: 1.
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   Number of Vref pins used: 0.
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+----------+----------------+------------+------------+------------+
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+----------+----------------+------------+------------+------------+
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| 1        | 0 / 33 (  0%)  | -          | -          | -          |
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| 2        | 1 / 32 (  3%)  | 2.5V       | -          | -          |
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| 3        | 14 / 33 ( 42%) | 2.5V       | -          | -          |
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| 7        | 0 / 32 (  0%)  | -          | -          | -          |
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+----------+----------------+------------+------------+------------+
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Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
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0 connections routed; 657 unrouted.
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Starting router resource preassignment
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Completed router resource preassignment. Real time: 22 secs
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*****************************************************************
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Info: NBR allows conflicts(one node used by more than one signal)
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      in the earlier iterations. In each iteration, it tries to
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      solve the conflicts while keeping the critical connections
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      be completed when no conflicts exist and all connections
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      are routed.
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Note: NBR uses a different method to calculate timing slacks. The
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      worst slack and total negative slack may not be the same as
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      your design.
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*****************************************************************
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Start NBR special constraint process at 01:08:52 01/18/17
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0(0.00%) conflict; 544(82.80%) untouched conns; 8380 (nbr) score;
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Level 2, iteration 1
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0(0.00%) conflict; 542(82.50%) untouched conns; 8800 (nbr) score;
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Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 23 secs
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Level 3, iteration 1
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0(0.00%) conflict; 523(79.60%) untouched conns; 8800 (nbr) score;
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Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 23 secs
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Level 4, iteration 1
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Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 23 secs
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Info: Initial congestion level at 75% usage is 0
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Level 1, iteration 1
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Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
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Level 2, iteration 1
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Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
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0(0.00%) conflict; 8(1.22%) untouched conns; 8800 (nbr) score;
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Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
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0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
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Level 4, iteration 1
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0(0.00%) conflict; 0(0.00%) untouched conn; 8800 (nbr) score;
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Estimated worst slack/total negative slack&lt;setup&gt;: -1.238ns/-8.800ns; real time: 24 secs
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Start NBR section for post-routing at 01:08:53 01/18/17
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End NBR router with 0 unrouted connection
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NBR Summary
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-----------
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  Number of unrouted connections : 0 (0.00%)
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  Number of connections with timing violations : 9 (1.37%)
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  Estimated worst slack&lt;setup&gt; : -1.238ns
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  Timing score&lt;setup&gt; : 7103
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-----------
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Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.
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Total CPU time 24 secs
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Completely routed.
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Timing score: 7103
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Dumping design to file DisplayDriverwDecoder_impl1.dir/5_1.ncd.
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PAR_SUMMARY::Run status = completed
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PAR_SUMMARY::Number of unrouted conns = 0
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PAR_SUMMARY::Worst  slack&lt;setup/&lt;ns&gt;&gt; = -1.238
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PAR_SUMMARY::Timing score&lt;setup/&lt;ns&gt;&gt; = 7.103
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PAR_SUMMARY::Worst  slack&lt;hold /&lt;ns&gt;&gt; = 0.178
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PAR_SUMMARY::Timing score&lt;hold /&lt;ns&gt;&gt; = 0.000
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PAR_SUMMARY::Number of errors = 0
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Total CPU  time to completion: 25 secs
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Total REAL time to completion: 26 secs
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par done!
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&amp;T Corp.   All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
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Copyright (c) 2001 Agere Systems   All rights reserved.
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Copyright (c) 2002-2016 Lattice Semiconductor Corporation,  All rights reserved.
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