OpenCores
URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_synplify.html] - Blame information for rev 5

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 5 liubenoff 
<HTML>
2 
<HEAD><TITLE>Synthesis Report</TITLE>
3 
<STYLE TYPE="text/css">
4 
<!--
5 
 body,pre{
    font-family:'Courier New', monospace;
    color: #000000;
    font-size:88%;
    background-color: #ffffff;
}
h1 {
    font-weight: bold;
    margin-top: 24px;
    margin-bottom: 10px;
    border-bottom: 3px solid #000;    font-size: 1em;
}
h2 {
    font-weight: bold;
    margin-top: 18px;
    margin-bottom: 5px;
    font-size: 0.90em;
}
h3 {
    font-weight: bold;
    margin-top: 12px;
    margin-bottom: 5px;
    font-size: 0.80em;
}
p {
    font-size:78%;
}
P.Table {
    margin-top: 4px;
    margin-bottom: 4px;
    margin-right: 4px;
    margin-left: 4px;
}
table
{
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    border-collapse: collapse;
}
th {
    font-weight:bold;
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    text-align:left;
    font-size:78%;
}
td {
    padding: 4px;
    border-width: 1px 1px 1px 1px;
    border-style: solid solid solid solid;
    border-color: black black black black;
    vertical-align:top;
    font-size:78%;
}
a {
    color:#013C9A;
    text-decoration:none;
}

a:visited {
    color:#013C9A;
}

a:hover, a:active {
    text-decoration:underline;
    color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
    font-size: 90%;
    font-style: italic;
}
6 
-->
7 
</STYLE>
8 
</HEAD>
9 
<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
10 
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016
11 
#install: C:\lscc\diamond\3.8_x64\synpbase
12 
#OS: Windows 8 6.2
13 
#Hostname: DESKTOP-1AUKF7V
14 
 
15 
# Fri Jan 13 00:54:37 2017
16 
 
17 
#Implementation: impl1
18 
 
19 
Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
20 
@N|Running in 64-bit mode
21 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
22 
 
23 
Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
24 
@N|Running in 64-bit mode
25 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
26 
 
27 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
28 
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
29 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
30 
VHDL syntax check successful!
31 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
32 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
33 
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
34 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
35 
Post processing for work.displaydriverwdecoder_top.arch
36 
Post processing for work.displaydriverwrapper.arch
37 
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
38 
 
39 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 71MB peak: 71MB)
40 
 
41 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
42 
 
43 
Process completed successfully.
44 
# Fri Jan 13 00:54:37 2017
45 
 
46 
###########################################################]
47 
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
48 
@N|Running in 64-bit mode
49 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
50 
 
51 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
52 
 
53 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
54 
 
55 
Process completed successfully.
56 
# Fri Jan 13 00:54:37 2017
57 
 
58 
###########################################################]
59 
@END
60 
 
61 
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
62 
 
63 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
64 
 
65 
Process completed successfully.
66 
# Fri Jan 13 00:54:37 2017
67 
 
68 
###########################################################]
69 
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
70 
@N|Running in 64-bit mode
71 
 
72 
 
73 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
74 
 
75 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
76 
 
77 
Process completed successfully.
78 
# Fri Jan 13 00:54:39 2017
79 
 
80 
###########################################################]
81 
Pre-mapping Report
82 
 
83 
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
84 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
85 
Product Version L-2016.03L-1
86 
 
87 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
88 
 
89 
 
90 
@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt
91 
Printing clock  summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt" file
92 
@N: MF248 |Running in 64-bit mode.
93 
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
94 
 
95 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
96 
 
97 
 
98 
 
99 
 
100 
 
101 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
102 
 
103 
 
104 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
105 
 
106 
 
107 
Number of ICG latches removed:  0
108 
Number of ICG latches not removed:      0
109 
syn_allowed_resources : blockrams=108  set on top level netlist DisplayDriverWrapper
110 
 
111 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
112 
 
113 
 
114 
 
115 
Clock Summary
116 
*****************
117 
 
118 
Start                        Requested     Requested     Clock        Clock                     Clock
119 
Clock                        Frequency     Period        Type         Group                     Load
120 
-----------------------------------------------------------------------------------------------------
121 
DisplayDriverWrapper|clk     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0     8
122 
 
123 
 
124 
 
125 
 
126 
 
127 
 
128 
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
129 
 
130 
None
131 
None
132 
 
133 
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
134 
 
135 
Pre-mapping successful!
136 
 
137 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
138 
 
139 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
140 
# Fri Jan 13 00:54:39 2017
141 
 
142 
###########################################################]
143 
Map & Optimize Report
144 
 
145 
Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
146 
 
147 
Product Version L-2016.03L-1
148 
 
149 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
150 
 
151 
 
152 
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
153 
 
154 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
155 
 
156 
 
157 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
158 
 
159 
 
160 
 
161 
 
162 
 
163 
 
164 
 
165 
 
166 
 
167 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
168 
 
169 
 
170 
 
171 
        None Found
172 
 
173 
@N: MT206 |Auto Constrain mode is enabled
174 
 
175 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
176 
 
177 
 
178 
 
179 
 
180 
 
181 
 
182 
 
183 
 
184 
 
185 
 
186 
 
187 
 
188 
 
189 
 
190 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
191 
 
192 
 
193 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
194 
 
195 
 
196 
 
197 
 
198 
 
199 
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
200 
 
201 
 
202 
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
203 
 
204 
Pass             CPU time               Worst Slack             Luts / Registers
205 
------------------------------------------------------------
206 
 
207 
 
208 
 
209 
 
210 
 
211 
 
212 
 
213 
 
214 
 
215 
@S |Clock Optimization Summary
216 
 
217 
 
218 
 
219 
 
220 
 
221 
0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
222 
 
223 
 
224 
============================== Non-Gated/Non-Generated Clocks ===============================
225 
 
226 
---------------------------------------------------------------------------------------------
227 
@K:CKID0001       clk                 port                   8          DDwD_Top.ascii_reg[6]
228 
 
229 
 
230 
 
231 
##### END OF CLOCK OPTIMIZATION REPORT ######]
232 
 
233 
 
234 
 
235 
 
236 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
237 
 
238 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
239 
 
240 
 
241 
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1.edi
242 
 
243 
 
244 
 
245 
 
246 
 
247 
 
248 
 
249 
 
250 
 
251 
 
252 
 
253 
 
254 
# Timing Report written on Fri Jan 13 00:54:42 2017
255 
#
256 
 
257 
 
258 
 
259 
Requested Frequency:    1220.4 MHz
260 
 
261 
 
262 
Constraint File(s):
263 
 
264 
 
265 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
266 
 
267 
 
268 
 
269 
 
270 
 
271 
 
272 
 
273 
 
274 
 
275 
 
276 
 
277 
------------------------------------------------------------------------------------------------------------------------------------
278 
 
279 
 
280 
 
281 
 
282 
 
283 
 
284 
 
285 
 
286 
*******************
287 
 
288 
Clocks                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
289 
-------------------------------------------------------------------------------------------------------------------------------------------
290 
 
291 
-------------------------------------------------------------------------------------------------------------------------------------------
292 
 
293 
===========================================================================================================================================
294 
 
295 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
296 
 
297 
 
298 
 
299 
Interface Information
300 
 
301 
 
302 
No IO constraint found
303 
 
304 
 
305 
 
306 
 
307 
 
308 
====================================
309 
 
310 
 
311 
 
312 
Starting Points with Worst Slack
313 
 
314 
 
315 
                          Starting                                                          Arrival
316 
 
317 
 
318 
--------------------------------------------------------------------------------------------------------------
319 
 
320 
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[1]     0.753       -0.145
321 
 
322 
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[3]     0.753       -0.145
323 
 
324 
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[5]     0.753       -0.145
325 
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[6]     0.753       -0.145
326 
DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[7]     0.753       -0.145
327 
==============================================================================================================
328 
 
329 
 
330 
 
331 
 
332 
 
333 
 
334 
Instance                  Reference                    Type        Pin     Net              Time         Slack
335 
 
336 
 
337 
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[0]     0.608        -0.145
338 
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[1]     0.608        -0.145
339 
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[2]     0.608        -0.145
340 
 
341 
 
342 
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[5]     0.608        -0.145
343 
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[6]     0.608        -0.145
344 
DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[7]     0.608        -0.145
345 
===============================================================================================================
346 
 
347 
 
348 
 
349 
Worst Path Information
350 
 
351 
 
352 
 
353 
Path information for path number 1:
354 
      Requested Period:                      0.819
355 
 
356 
 
357 
    = Required time:                         0.608
358 
 
359 
    - Propagation time:                      0.753
360 
    - Clock delay at starting point:         0.000 (ideal)
361 
    = Slack (critical) :                     -0.145
362 
 
363 
    Number of logic level(s):                0
364 
 
365 
 
366 
 
367 
 
368 
 
369 
Instance / Net                        Pin      Pin               Arrival     No. of
370 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
371 
 
372 
DDwD_Top.ascii_reg[0]     FD1S3IX     Q        Out     0.753     0.753       -
373 
ascii_reg[0]              Net         -        -       -         -           1
374 
DDwD_Top.ascii_reg[0]     FD1S3IX     D        In      0.000     0.753       -
375 
=======================================================================================
376 
 
377 
 
378 
Path information for path number 2:
379 
      Requested Period:                      0.819
380 
 
381 
 
382 
 
383 
 
384 
    - Propagation time:                      0.753
385 
 
386 
    = Slack (critical) :                     -0.145
387 
 
388 
 
389 
 
390 
    Ending point:                            DDwD_Top.ascii_reg[1] / D
391 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
392 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
393 
 
394 
 
395 
 
396 
---------------------------------------------------------------------------------------
397 
DDwD_Top.ascii_reg[1]     FD1S3JX     Q        Out     0.753     0.753       -
398 
 
399 
DDwD_Top.ascii_reg[1]     FD1S3JX     D        In      0.000     0.753       -
400 
=======================================================================================
401 
 
402 
 
403 
Path information for path number 3:
404 
      Requested Period:                      0.819
405 
    - Setup time:                            0.211
406 
    + Clock delay at ending point:           0.000 (ideal)
407 
    = Required time:                         0.608
408 
 
409 
    - Propagation time:                      0.753
410 
    - Clock delay at starting point:         0.000 (ideal)
411 
    = Slack (critical) :                     -0.145
412 
 
413 
 
414 
    Starting point:                          DDwD_Top.ascii_reg[2] / Q
415 
    Ending point:                            DDwD_Top.ascii_reg[2] / D
416 
 
417 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
418 
 
419 
Instance / Net                        Pin      Pin               Arrival     No. of
420 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
421 
---------------------------------------------------------------------------------------
422 
DDwD_Top.ascii_reg[2]     FD1S3IX     Q        Out     0.753     0.753       -
423 
ascii_reg[2]              Net         -        -       -         -           1
424 
DDwD_Top.ascii_reg[2]     FD1S3IX     D        In      0.000     0.753       -
425 
=======================================================================================
426 
 
427 
 
428 
Path information for path number 4:
429 
      Requested Period:                      0.819
430 
 
431 
 
432 
 
433 
 
434 
    - Propagation time:                      0.753
435 
 
436 
 
437 
 
438 
    Number of logic level(s):                0
439 
    Starting point:                          DDwD_Top.ascii_reg[3] / Q
440 
    Ending point:                            DDwD_Top.ascii_reg[3] / D
441 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
442 
 
443 
 
444 
Instance / Net                        Pin      Pin               Arrival     No. of
445 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
446 
 
447 
DDwD_Top.ascii_reg[3]     FD1S3IX     Q        Out     0.753     0.753       -
448 
ascii_reg[3]              Net         -        -       -         -           1
449 
DDwD_Top.ascii_reg[3]     FD1S3IX     D        In      0.000     0.753       -
450 
=======================================================================================
451 
 
452 
 
453 
Path information for path number 5:
454 
      Requested Period:                      0.819
455 
    - Setup time:                            0.211
456 
    + Clock delay at ending point:           0.000 (ideal)
457 
    = Required time:                         0.608
458 
 
459 
    - Propagation time:                      0.753
460 
 
461 
 
462 
 
463 
    Number of logic level(s):                0
464 
    Starting point:                          DDwD_Top.ascii_reg[4] / Q
465 
    Ending point:                            DDwD_Top.ascii_reg[4] / D
466 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
467 
 
468 
 
469 
Instance / Net                        Pin      Pin               Arrival     No. of
470 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
471 
 
472 
DDwD_Top.ascii_reg[4]     FD1S3JX     Q        Out     0.753     0.753       -
473 
ascii_reg[4]              Net         -        -       -         -           1
474 
DDwD_Top.ascii_reg[4]     FD1S3JX     D        In      0.000     0.753       -
475 
=======================================================================================
476 
 
477 
 
478 
 
479 
##### END OF TIMING REPORT #####]
480 
 
481 
Constraints that could not be applied
482 
None
483 
 
484 
Finished final timing analysis (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
485 
 
486 
 
487 
Finished timing report (Real Time elapsed 0h:00m:02s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
488 
 
489 
---------------------------------------
490 
Resource Usage Report
491 
Part: lfe5um5g_45f-8
492 
 
493 
Register bits: 8 of 43848 (0%)
494 
PIC Latch:       0
495 
I/O cells:       18
496 
 
497 
 
498 
Details:
499 
FD1S3IX:        5
500 
FD1S3JX:        3
501 
GSR:            1
502 
 
503 
OB:             16
504 
PUR:            1
505 
VHI:            2
506 
VLO:            1
507 
false:          1
508 
Mapper successful!
509 
 
510 
 
511 
 
512 
Process took 0h:00m:02s realtime, 0h:00m:01s cputime
513 
# Fri Jan 13 00:54:42 2017
514 
 
515 
###########################################################]
516 
 
517 
 
518 
 
519 
<BR>
520 
<BR>
521 
 
522 
<BR>
523 
<BR>
524 
<BR>
525 
<BR>
526 
<BR>
527 
 
528 
<BR>
529 
<BR>
530 
<BR>
531 
<BR>
532 
<BR>
533 
<BR>
534 
<BR>
535 
 
536 
 
537 
<BR>
538 
<BR>
539 
<BR>
540 
<BR>
541 
<BR>
542 
 
543 
<BR>
544 
<BR>
545 
<BR>
546 
 
547 
<BR>
548 
<BR>
549 
<BR>
550 
<BR>
551 
<BR>
552 
 
553 
<BR>
554 
<BR>
555 
<BR>
556 
<BR>
557 
<BR>
558 
<BR>
559 
<BR>
560 
 
561 
 
562 
 
563 
<BR>
564 
 
565 
<BR>
566 
<BR>
567 
 
568 
<BR>
569 
 
570 
 
571 
</HTML>
572 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.