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<HTML>
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<HEAD><TITLE>Synthesis Report</TITLE>
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body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
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font-weight: bold;
margin-top: 24px;
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margin-top: 18px;
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table
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padding: 4px;
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text-align:left;
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td {
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font-size:78%;
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a {
color:#013C9A;
text-decoration:none;
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a:visited {
color:#013C9A;
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a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
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background-color: #00ff00;
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-->
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</STYLE>
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</HEAD>
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
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#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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# Tue Jan 17 01:19:09 2017
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#Implementation: impl1
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Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
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File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
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VHDL syntax check successful!
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Compiler output is up to date. No re-compile necessary
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
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@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
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@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
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@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
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Post processing for work.rom128x1a.syn_black_box
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Post processing for work.distromasciidecoder.structure
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Post processing for work.asciidecoder.arch
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Post processing for work.displaydriverwdecoder_top.arch
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Post processing for work.displaydriverwrapper.arch
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@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_5. Make sure that there are no unused intermediate registers.
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@W: CL169 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":54:4:54:5|Pruning unused register bttn_state_fifo_5(3 downto 0). Make sure that there are no unused intermediate registers.
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 72MB peak: 73MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Jan 17 01:19:09 2017
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###########################################################]
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Jan 17 01:19:09 2017
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###########################################################]
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Tue Jan 17 01:19:11 2017
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###########################################################]
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Pre-mapping Report
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6 |
liubenoff |
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@A: MF827 |No constraint file specified.
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@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
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liubenoff |
ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Clock Summary
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*****************
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Start Requested Requested Clock Clock Clock
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Clock Frequency Period Type Group Load
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--------------------------------------------------------------------------------------------------------
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DisplayDriverWrapper|button 918.9 MHz 1.088 inferred Autoconstr_clkgroup_0 8
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========================================================================================================
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@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found inferred clock DisplayDriverWrapper|button which controls 8 sequential elements including symbol_scan_cntr[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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Finished Pre Mapping Phase.
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Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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None
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Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pre-mapping successful!
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At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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# Tue Jan 17 01:19:11 2017
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###########################################################]
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Map & Optimize Report
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Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
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Product Version L-2016.03L-1
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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None Found
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@N: MT206 |Auto Constrain mode is enabled
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":74:4:74:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pass CPU time Worst Slack Luts / Registers
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------------------------------------------------------------
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2 0h:00m:00s -0.70ns 1 / 8
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Timing driven replication report
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Added 0 LUTs via timing driven replication
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3 0h:00m:00s -0.64ns 1 / 9
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@S |Clock Optimization Summary
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#### START OF CLOCK OPTIMIZATION REPORT #####[
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1 non-gated/non-generated clock tree(s) driving 9 clock pin(s) of sequential element(s)
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0 instances converted, 0 sequential instances remain driven by gated/generated clocks
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============================= Non-Gated/Non-Generated Clocks ==============================
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Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
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@K:CKID0001 button port 9 symbol_scan_cntr[0]
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Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_m.srm
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|
| 265 |
|
|
|
| 266 |
|
|
Writing EDIF Netlist and constraint files
|
| 267 |
|
|
|
| 268 |
|
|
|
| 269 |
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
| 270 |
|
|
|
| 271 |
|
|
|
| 272 |
|
|
|
| 273 |
|
|
|
| 274 |
|
|
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
| 275 |
|
|
|
| 276 |
6 |
liubenoff |
@W: MT420 |Found inferred clock DisplayDriverWrapper|button with period 2.25ns. Please declare a user-defined clock on object "p:button"
|
| 277 |
5 |
liubenoff |
|
| 278 |
|
|
|
| 279 |
|
|
|
| 280 |
|
|
|
| 281 |
|
|
#
|
| 282 |
|
|
|
| 283 |
|
|
|
| 284 |
|
|
Top view: DisplayDriverWrapper
|
| 285 |
|
|
|
| 286 |
|
|
|
| 287 |
|
|
Paths requested: 5
|
| 288 |
|
|
|
| 289 |
|
|
|
| 290 |
|
|
|
| 291 |
|
|
|
| 292 |
|
|
|
| 293 |
|
|
|
| 294 |
|
|
|
| 295 |
|
|
|
| 296 |
|
|
*******************
|
| 297 |
|
|
|
| 298 |
|
|
|
| 299 |
|
|
Worst slack in design: -0.398
|
| 300 |
|
|
|
| 301 |
|
|
|
| 302 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
| 303 |
|
|
|
| 304 |
|
|
DisplayDriverWrapper|button 443.5 MHz 377.0 MHz 2.255 2.652 -0.398 inferred Autoconstr_clkgroup_0
|
| 305 |
|
|
=====================================================================================================================================
|
| 306 |
6 |
liubenoff |
|
| 307 |
|
|
|
| 308 |
|
|
|
| 309 |
|
|
|
| 310 |
|
|
|
| 311 |
|
|
Clock Relationships
|
| 312 |
5 |
liubenoff |
|
| 313 |
6 |
liubenoff |
|
| 314 |
|
|
|
| 315 |
|
|
-------------------------------------------------------------------------------------------------------------------------------------------------
|
| 316 |
|
|
|
| 317 |
5 |
liubenoff |
-------------------------------------------------------------------------------------------------------------------------------------------------
|
| 318 |
|
|
|
| 319 |
|
|
=================================================================================================================================================
|
| 320 |
|
|
|
| 321 |
6 |
liubenoff |
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
| 322 |
5 |
liubenoff |
|
| 323 |
|
|
|
| 324 |
|
|
|
| 325 |
|
|
Interface Information
|
| 326 |
|
|
|
| 327 |
|
|
|
| 328 |
|
|
No IO constraint found
|
| 329 |
|
|
|
| 330 |
6 |
liubenoff |
|
| 331 |
5 |
liubenoff |
|
| 332 |
|
|
|
| 333 |
|
|
|
| 334 |
6 |
liubenoff |
====================================
|
| 335 |
|
|
|
| 336 |
|
|
|
| 337 |
|
|
|
| 338 |
|
|
Starting Points with Worst Slack
|
| 339 |
5 |
liubenoff |
|
| 340 |
|
|
|
| 341 |
|
|
Starting Arrival
|
| 342 |
|
|
|
| 343 |
|
|
|
| 344 |
|
|
--------------------------------------------------------------------------------------------------------------------------------
|
| 345 |
|
|
|
| 346 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[2] 0.933 -0.398
|
| 347 |
|
|
|
| 348 |
6 |
liubenoff |
symbol_scan_cntr[4] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[4] 0.933 -0.339
|
| 349 |
5 |
liubenoff |
|
| 350 |
|
|
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[6] 0.933 -0.280
|
| 351 |
|
|
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr_fast[0] 0.753 -0.277
|
| 352 |
|
|
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX Q symbol_scan_cntr[7] 0.798 0.570
|
| 353 |
|
|
================================================================================================================================
|
| 354 |
|
|
|
| 355 |
6 |
liubenoff |
|
| 356 |
5 |
liubenoff |
|
| 357 |
|
|
|
| 358 |
6 |
liubenoff |
|
| 359 |
5 |
liubenoff |
|
| 360 |
6 |
liubenoff |
Instance Reference Type Pin Net Time Slack
|
| 361 |
5 |
liubenoff |
|
| 362 |
|
|
|
| 363 |
|
|
symbol_scan_cntr[7] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[7] 2.044 -0.398
|
| 364 |
6 |
liubenoff |
symbol_scan_cntr[5] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[5] 2.044 -0.339
|
| 365 |
5 |
liubenoff |
symbol_scan_cntr[6] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[6] 2.044 -0.339
|
| 366 |
|
|
|
| 367 |
|
|
|
| 368 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[1] 2.044 -0.100
|
| 369 |
6 |
liubenoff |
symbol_scan_cntr[2] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[2] 2.044 -0.100
|
| 370 |
5 |
liubenoff |
symbol_scan_cntr[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
|
| 371 |
|
|
symbol_scan_cntr_fast[0] DisplayDriverWrapper|button FD1S3DX D symbol_scan_cntr_s[0] 2.044 0.570
|
| 372 |
|
|
==============================================================================================================================
|
| 373 |
|
|
|
| 374 |
|
|
|
| 375 |
|
|
|
| 376 |
|
|
|
| 377 |
|
|
|
| 378 |
|
|
|
| 379 |
|
|
|
| 380 |
|
|
Path information for path number 1:
|
| 381 |
|
|
|
| 382 |
|
|
|
| 383 |
6 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 384 |
5 |
liubenoff |
|
| 385 |
6 |
liubenoff |
|
| 386 |
|
|
- Propagation time: 2.442
|
| 387 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 388 |
|
|
= Slack (critical) : -0.398
|
| 389 |
|
|
|
| 390 |
5 |
liubenoff |
|
| 391 |
|
|
|
| 392 |
|
|
|
| 393 |
|
|
|
| 394 |
|
|
|
| 395 |
|
|
|
| 396 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 397 |
|
|
|
| 398 |
6 |
liubenoff |
-------------------------------------------------------------------------------------------
|
| 399 |
|
|
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
|
| 400 |
|
|
symbol_scan_cntr[1] Net - - - - 15
|
| 401 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
| 402 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
| 403 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 404 |
5 |
liubenoff |
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
| 405 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
| 406 |
|
|
|
| 407 |
|
|
|
| 408 |
|
|
|
| 409 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
| 410 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
| 411 |
|
|
|
| 412 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
| 413 |
|
|
|
| 414 |
|
|
|
| 415 |
|
|
|
| 416 |
|
|
|
| 417 |
6 |
liubenoff |
Path information for path number 2:
|
| 418 |
5 |
liubenoff |
Requested Period: 2.255
|
| 419 |
|
|
|
| 420 |
|
|
|
| 421 |
|
|
|
| 422 |
|
|
|
| 423 |
|
|
- Propagation time: 2.442
|
| 424 |
|
|
|
| 425 |
6 |
liubenoff |
= Slack (critical) : -0.398
|
| 426 |
|
|
|
| 427 |
|
|
Number of logic level(s): 4
|
| 428 |
|
|
Starting point: symbol_scan_cntr[2] / Q
|
| 429 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
| 430 |
|
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
| 431 |
|
|
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
| 432 |
|
|
|
| 433 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 434 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 435 |
|
|
-------------------------------------------------------------------------------------------
|
| 436 |
|
|
symbol_scan_cntr[2] FD1S3DX Q Out 0.933 0.933 -
|
| 437 |
|
|
symbol_scan_cntr[2] Net - - - - 15
|
| 438 |
5 |
liubenoff |
|
| 439 |
|
|
|
| 440 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 441 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
| 442 |
|
|
|
| 443 |
6 |
liubenoff |
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 444 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
| 445 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
| 446 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
| 447 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
| 448 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
| 449 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
| 450 |
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.442 -
|
| 451 |
|
|
===========================================================================================
|
| 452 |
|
|
|
| 453 |
|
|
|
| 454 |
|
|
Path information for path number 3:
|
| 455 |
|
|
Requested Period: 2.255
|
| 456 |
|
|
- Setup time: 0.211
|
| 457 |
5 |
liubenoff |
|
| 458 |
|
|
|
| 459 |
|
|
|
| 460 |
|
|
- Propagation time: 2.382
|
| 461 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 462 |
|
|
|
| 463 |
|
|
|
| 464 |
|
|
Number of logic level(s): 3
|
| 465 |
6 |
liubenoff |
Starting point: symbol_scan_cntr[3] / Q
|
| 466 |
5 |
liubenoff |
Ending point: symbol_scan_cntr[7] / D
|
| 467 |
|
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
| 468 |
6 |
liubenoff |
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
| 469 |
5 |
liubenoff |
|
| 470 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 471 |
5 |
liubenoff |
Name Type Name Dir Delay Time Fan Out(s)
|
| 472 |
6 |
liubenoff |
-------------------------------------------------------------------------------------------
|
| 473 |
5 |
liubenoff |
|
| 474 |
6 |
liubenoff |
symbol_scan_cntr[3] Net - - - - 15
|
| 475 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C A0 In 0.000 0.933 -
|
| 476 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.784 1.717 -
|
| 477 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 478 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
|
| 479 |
5 |
liubenoff |
|
| 480 |
6 |
liubenoff |
symbol_scan_cntr_cry[6] Net - - - - 1
|
| 481 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
|
| 482 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.382 -
|
| 483 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
| 484 |
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
|
| 485 |
|
|
===========================================================================================
|
| 486 |
|
|
|
| 487 |
|
|
|
| 488 |
|
|
Path information for path number 4:
|
| 489 |
|
|
Requested Period: 2.255
|
| 490 |
|
|
- Setup time: 0.211
|
| 491 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 492 |
|
|
= Required time: 2.044
|
| 493 |
|
|
|
| 494 |
|
|
- Propagation time: 2.382
|
| 495 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 496 |
|
|
= Slack (non-critical) : -0.339
|
| 497 |
|
|
|
| 498 |
|
|
Number of logic level(s): 3
|
| 499 |
5 |
liubenoff |
|
| 500 |
|
|
|
| 501 |
|
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
| 502 |
6 |
liubenoff |
The end point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
| 503 |
5 |
liubenoff |
|
| 504 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 505 |
6 |
liubenoff |
Name Type Name Dir Delay Time Fan Out(s)
|
| 506 |
5 |
liubenoff |
|
| 507 |
6 |
liubenoff |
symbol_scan_cntr[4] FD1S3DX Q Out 0.933 0.933 -
|
| 508 |
5 |
liubenoff |
symbol_scan_cntr[4] Net - - - - 15
|
| 509 |
6 |
liubenoff |
symbol_scan_cntr_cry_0[3] CCU2C A1 In 0.000 0.933 -
|
| 510 |
5 |
liubenoff |
|
| 511 |
6 |
liubenoff |
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 512 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.717 -
|
| 513 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.776 -
|
| 514 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
| 515 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.776 -
|
| 516 |
5 |
liubenoff |
|
| 517 |
6 |
liubenoff |
symbol_scan_cntr_s[7] Net - - - - 1
|
| 518 |
|
|
symbol_scan_cntr[7] FD1S3DX D In 0.000 2.382 -
|
| 519 |
|
|
===========================================================================================
|
| 520 |
|
|
|
| 521 |
|
|
|
| 522 |
|
|
Path information for path number 5:
|
| 523 |
|
|
Requested Period: 2.255
|
| 524 |
|
|
- Setup time: 0.211
|
| 525 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
| 526 |
|
|
= Required time: 2.044
|
| 527 |
|
|
|
| 528 |
|
|
- Propagation time: 2.382
|
| 529 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
| 530 |
|
|
= Slack (non-critical) : -0.339
|
| 531 |
|
|
|
| 532 |
|
|
Number of logic level(s): 3
|
| 533 |
|
|
Starting point: symbol_scan_cntr[1] / Q
|
| 534 |
|
|
Ending point: symbol_scan_cntr[5] / D
|
| 535 |
|
|
The start point is clocked by DisplayDriverWrapper|button [rising] on pin CK
|
| 536 |
5 |
liubenoff |
|
| 537 |
|
|
|
| 538 |
|
|
Instance / Net Pin Pin Arrival No. of
|
| 539 |
6 |
liubenoff |
Name Type Name Dir Delay Time Fan Out(s)
|
| 540 |
5 |
liubenoff |
-------------------------------------------------------------------------------------------
|
| 541 |
|
|
symbol_scan_cntr[1] FD1S3DX Q Out 0.933 0.933 -
|
| 542 |
6 |
liubenoff |
symbol_scan_cntr[1] Net - - - - 15
|
| 543 |
5 |
liubenoff |
|
| 544 |
6 |
liubenoff |
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
| 545 |
5 |
liubenoff |
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 546 |
6 |
liubenoff |
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
| 547 |
5 |
liubenoff |
|
| 548 |
6 |
liubenoff |
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 549 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
| 550 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.382 -
|
| 551 |
|
|
symbol_scan_cntr_s[5] Net - - - - 1
|
| 552 |
|
|
symbol_scan_cntr[5] FD1S3DX D In 0.000 2.382 -
|
| 553 |
5 |
liubenoff |
|
| 554 |
6 |
liubenoff |
|
| 555 |
|
|
|
| 556 |
|
|
|
| 557 |
|
|
##### END OF TIMING REPORT #####]
|
| 558 |
|
|
|
| 559 |
|
|
Constraints that could not be applied
|
| 560 |
|
|
None
|
| 561 |
|
|
|
| 562 |
|
|
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
| 563 |
|
|
|
| 564 |
|
|
|
| 565 |
|
|
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
| 566 |
|
|
|
| 567 |
|
|
---------------------------------------
|
| 568 |
|
|
Resource Usage Report
|
| 569 |
|
|
Part: lfe5um5g_45f-8
|
| 570 |
5 |
liubenoff |
|
| 571 |
|
|
|
| 572 |
|
|
PIC Latch: 0
|
| 573 |
6 |
liubenoff |
I/O cells: 18
|
| 574 |
5 |
liubenoff |
|
| 575 |
|
|
|
| 576 |
6 |
liubenoff |
Details:
|
| 577 |
5 |
liubenoff |
|
| 578 |
6 |
liubenoff |
FD1S3DX: 9
|
| 579 |
5 |
liubenoff |
GSR: 1
|
| 580 |
6 |
liubenoff |
IB: 2
|
| 581 |
5 |
liubenoff |
|
| 582 |
6 |
liubenoff |
OB: 16
|
| 583 |
|
|
PUR: 1
|
| 584 |
|
|
ROM128X1A: 14
|
| 585 |
|
|
VHI: 1
|
| 586 |
|
|
VLO: 1
|
| 587 |
5 |
liubenoff |
|
| 588 |
6 |
liubenoff |
|
| 589 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
| 590 |
|
|
|
| 591 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 592 |
|
|
# Tue Jan 17 01:19:13 2017
|
| 593 |
|
|
|
| 594 |
|
|
###########################################################]
|
| 595 |
|
|
|
| 596 |
|
|
|
| 597 |
|
|
|
| 598 |
|
|
<BR>
|
| 599 |
|
|
<BR>
|
| 600 |
|
|
<BR>
|
| 601 |
|
|
<BR>
|
| 602 |
|
|
<BR>
|
| 603 |
|
|
<BR>
|
| 604 |
5 |
liubenoff |
|
| 605 |
|
|
|
| 606 |
|
|
<BR>
|
| 607 |
6 |
liubenoff |
<BR>
|
| 608 |
5 |
liubenoff |
<BR>
|
| 609 |
|
|
<BR>
|
| 610 |
6 |
liubenoff |
<BR>
|
| 611 |
5 |
liubenoff |
|
| 612 |
6 |
liubenoff |
<BR>
|
| 613 |
5 |
liubenoff |
<BR>
|
| 614 |
6 |
liubenoff |
<BR>
|
| 615 |
5 |
liubenoff |
|
| 616 |
6 |
liubenoff |
<BR>
|
| 617 |
|
|
<BR>
|
| 618 |
|
|
<BR>
|
| 619 |
|
|
<BR>
|
| 620 |
|
|
<BR>
|
| 621 |
5 |
liubenoff |
|
| 622 |
6 |
liubenoff |
<BR>
|
| 623 |
|
|
<BR>
|
| 624 |
|
|
<BR>
|
| 625 |
|
|
<BR>
|
| 626 |
|
|
<BR>
|
| 627 |
|
|
<BR>
|
| 628 |
|
|
<BR>
|
| 629 |
|
|
<BR>
|
| 630 |
|
|
<BR>
|
| 631 |
|
|
<BR>
|
| 632 |
|
|
<BR>
|
| 633 |
|
|
<BR>
|
| 634 |
|
|
<BR>
|
| 635 |
|
|
<BR>
|
| 636 |
|
|
<BR>
|
| 637 |
|
|
<BR>
|
| 638 |
5 |
liubenoff |
|
| 639 |
|
|
|
| 640 |
|
|
|
| 641 |
|
|
<BR>
|
| 642 |
|
|
|
| 643 |
|
|
<BR>
|
| 644 |
|
|
<BR>
|
| 645 |
|
|
|
| 646 |
6 |
liubenoff |
<BR>
|
| 647 |
5 |
liubenoff |
|
| 648 |
|
|
|
| 649 |
6 |
liubenoff |
</BODY>
|
| 650 |
5 |
liubenoff |
|
| 651 |
|
|
|
