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<HTML>
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<HEAD><TITLE>Synthesis Report</TITLE>
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<!--
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body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
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h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
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h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
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p {
font-size:78%;
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P.Table {
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margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
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border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
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}
th {
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padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
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td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
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a {
color:#013C9A;
text-decoration:none;
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a:visited {
color:#013C9A;
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a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
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.pass
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background-color: #00ff00;
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background-color: #ff0000;
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.comment
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font-size: 90%;
font-style: italic;
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-->
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</STYLE>
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</HEAD>
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<PRE><A name="Syn"></A><B><U><big>Synthesis Report</big></U></B>
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#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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# Wed Jan 18 01:08:13 2017
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#Implementation: impl1
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Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Top entity is set to display_driver_wrapper.
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File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd changed - recompiling
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd changed - recompiling
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VHDL syntax check successful!
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd changed - recompiling
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:28|Synthesizing work.display_driver_wrapper.arch.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
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@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":42:11:42:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:19|Synthesizing work.ascii_decoder.arch.
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\decoder_table_dist_rom_impl\decoder_table_dist_rom\decoder_table_dist_rom.vhd":12:7:12:28|Synthesizing work.decoder_table_dist_rom.structure.
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@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
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Post processing for work.rom128x1a.syn_black_box
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Post processing for work.decoder_table_dist_rom.structure
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Post processing for work.ascii_decoder.arch
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Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
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Post processing for work.display_driver_wrapper.arch
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
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At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Jan 18 01:08:13 2017
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###########################################################]
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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###########################################################]
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@END
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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# Wed Jan 18 01:08:13 2017
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###########################################################]
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\DisplayDriverwDecoder_impl1_comp.srs changed - recompiling
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
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###########################################################]
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Pre-mapping Report
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Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Product Version L-2016.03L-1
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@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\DisplayDriverwDecoder_impl1_scck.rpt
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
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ICG Latch Removal Summary:
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Number of ICG latches removed: 0
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Number of ICG latches not removed: 0
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syn_allowed_resources : blockrams=108 set on top level netlist display_driver_wrapper
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Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Clock Summary
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*****************
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Start Requested Requested Clock Clock Clock
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Clock Frequency Period Type Group Load
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-------------------------------------------------------------------------------------------------------------------------------------------------------------
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display_driver_wrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from display_driver_wrapper|clk) Autoconstr_clkgroup_0 8
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=============================================================================================================================================================
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@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":52:8:52:9|Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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Finished Pre Mapping Phase.
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None
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None
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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###########################################################]
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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@N: MF248 |Running in 64-bit mode.
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 101MB)
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Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Available hyper_sources - for debug and ip models
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@N: MT206 |Auto Constrain mode is enabled
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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Pass CPU time Worst Slack Luts / Registers
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------------------------------------------------------------
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2 0h:00m:00s -0.76ns 6 / 13
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3 0h:00m:00s -0.62ns 7 / 13
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Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
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@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
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Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
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@N: MT611 :|Automatically generated clock display_driver_wrapper|bttn_state_derived_clock is not used and is being removed
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@S |Clock Optimization Summary
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#### START OF CLOCK OPTIMIZATION REPORT #####[
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1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
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0 gated/generated clock tree(s) driving 0 clock pin(s) of sequential element(s)
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8 instances converted, 0 sequential instances remain driven by gated/generated clocks
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=========================== Non-Gated/Non-Generated Clocks ============================
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---------------------------------------------------------------------------------------
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@K:CKID0001 clk port 13 bttn_state
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Finished Writing Netlist Databases (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 139MB peak: 141MB)
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L-2016.03L-1
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Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
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Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
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@W: MT420 |Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
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# Timing Report written on Wed Jan 18 01:08:17 2017
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Wire load mode: top
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@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
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|
286 |
|
|
|
287 |
|
|
|
288 |
|
|
|
289 |
|
|
|
290 |
9 |
liubenoff |
Performance Summary
|
291 |
5 |
liubenoff |
|
292 |
|
|
|
293 |
|
|
|
294 |
|
|
|
295 |
|
|
|
296 |
|
|
Requested Estimated Requested Estimated Clock Clock
|
297 |
|
|
|
298 |
|
|
|
299 |
|
|
display_driver_wrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
|
300 |
|
|
|
301 |
|
|
|
302 |
|
|
|
303 |
9 |
liubenoff |
|
304 |
|
|
|
305 |
5 |
liubenoff |
|
306 |
9 |
liubenoff |
Clock Relationships
|
307 |
6 |
liubenoff |
|
308 |
|
|
|
309 |
9 |
liubenoff |
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
310 |
|
|
|
311 |
5 |
liubenoff |
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
312 |
|
|
|
313 |
|
|
display_driver_wrapper|clk display_driver_wrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
|
314 |
|
|
|
315 |
6 |
liubenoff |
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
316 |
5 |
liubenoff |
|
317 |
9 |
liubenoff |
|
318 |
5 |
liubenoff |
|
319 |
|
|
|
320 |
|
|
Interface Information
|
321 |
|
|
|
322 |
|
|
|
323 |
|
|
No IO constraint found
|
324 |
|
|
|
325 |
9 |
liubenoff |
|
326 |
5 |
liubenoff |
|
327 |
9 |
liubenoff |
====================================
|
328 |
5 |
liubenoff |
|
329 |
9 |
liubenoff |
====================================
|
330 |
|
|
|
331 |
|
|
|
332 |
|
|
|
333 |
|
|
Starting Points with Worst Slack
|
334 |
5 |
liubenoff |
|
335 |
|
|
|
336 |
|
|
Starting Arrival
|
337 |
|
|
|
338 |
|
|
|
339 |
|
|
---------------------------------------------------------------------------------------------------------------------
|
340 |
|
|
|
341 |
|
|
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
|
342 |
|
|
|
343 |
9 |
liubenoff |
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
|
344 |
5 |
liubenoff |
|
345 |
|
|
symbol_scan_cntr[5] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
|
346 |
|
|
symbol_scan_cntr[6] display_driver_wrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
|
347 |
|
|
bttn_state_fifo[3] display_driver_wrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
|
348 |
|
|
bttn_state display_driver_wrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
|
349 |
|
|
|
350 |
9 |
liubenoff |
=====================================================================================================================
|
351 |
5 |
liubenoff |
|
352 |
|
|
|
353 |
6 |
liubenoff |
Ending Points with Worst Slack
|
354 |
5 |
liubenoff |
|
355 |
9 |
liubenoff |
|
356 |
5 |
liubenoff |
|
357 |
|
|
|
358 |
|
|
Clock
|
359 |
9 |
liubenoff |
----------------------------------------------------------------------------------------------------------------------------------
|
360 |
5 |
liubenoff |
symbol_scan_cntr[7] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
|
361 |
|
|
|
362 |
|
|
|
363 |
9 |
liubenoff |
symbol_scan_cntr[3] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
|
364 |
|
|
symbol_scan_cntr[4] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
|
365 |
5 |
liubenoff |
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
|
366 |
|
|
symbol_scan_cntr[2] display_driver_wrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
|
367 |
|
|
symbol_scan_cntr[0] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
368 |
|
|
symbol_scan_cntr[1] display_driver_wrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
369 |
|
|
|
370 |
|
|
==================================================================================================================================
|
371 |
|
|
|
372 |
|
|
|
373 |
|
|
|
374 |
|
|
Worst Path Information
|
375 |
|
|
***********************
|
376 |
|
|
|
377 |
|
|
|
378 |
9 |
liubenoff |
Path information for path number 1:
|
379 |
5 |
liubenoff |
|
380 |
9 |
liubenoff |
- Setup time: 0.211
|
381 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
382 |
|
|
= Required time: 2.094
|
383 |
|
|
|
384 |
|
|
- Propagation time: 2.501
|
385 |
5 |
liubenoff |
|
386 |
|
|
|
387 |
|
|
|
388 |
|
|
|
389 |
|
|
|
390 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
391 |
|
|
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
392 |
|
|
|
393 |
9 |
liubenoff |
|
394 |
|
|
Instance / Net Pin Pin Arrival No. of
|
395 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
396 |
|
|
-------------------------------------------------------------------------------------------
|
397 |
|
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
398 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
399 |
5 |
liubenoff |
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
400 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
401 |
|
|
|
402 |
|
|
|
403 |
|
|
|
404 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
405 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
406 |
|
|
|
407 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
408 |
|
|
|
409 |
|
|
|
410 |
|
|
|
411 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
|
412 |
9 |
liubenoff |
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
|
413 |
5 |
liubenoff |
symbol_scan_cntr_s[7] Net - - - - 1
|
414 |
|
|
|
415 |
|
|
|
416 |
|
|
|
417 |
|
|
|
418 |
|
|
Path information for path number 2:
|
419 |
|
|
|
420 |
9 |
liubenoff |
- Setup time: 0.211
|
421 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
422 |
|
|
= Required time: 2.094
|
423 |
|
|
|
424 |
|
|
- Propagation time: 2.442
|
425 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
426 |
|
|
= Slack (non-critical) : -0.348
|
427 |
|
|
|
428 |
|
|
Number of logic level(s): 4
|
429 |
|
|
Starting point: symbol_scan_cntr[1] / Q
|
430 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
431 |
|
|
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
432 |
|
|
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
433 |
|
|
|
434 |
|
|
Instance / Net Pin Pin Arrival No. of
|
435 |
5 |
liubenoff |
|
436 |
|
|
|
437 |
|
|
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
|
438 |
|
|
symbol_scan_cntr[1] Net - - - - 15
|
439 |
|
|
|
440 |
9 |
liubenoff |
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
441 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
442 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
443 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
444 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
445 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
446 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
447 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
448 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
449 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
450 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
451 |
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
452 |
|
|
===========================================================================================
|
453 |
|
|
|
454 |
|
|
|
455 |
5 |
liubenoff |
|
456 |
|
|
|
457 |
|
|
|
458 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
459 |
|
|
= Required time: 2.094
|
460 |
|
|
|
461 |
|
|
|
462 |
|
|
- Clock delay at starting point: 0.000 (ideal)
|
463 |
9 |
liubenoff |
= Slack (non-critical) : -0.348
|
464 |
5 |
liubenoff |
|
465 |
|
|
Number of logic level(s): 4
|
466 |
9 |
liubenoff |
Starting point: symbol_scan_cntr[2] / Q
|
467 |
5 |
liubenoff |
|
468 |
9 |
liubenoff |
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
469 |
5 |
liubenoff |
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
470 |
9 |
liubenoff |
|
471 |
5 |
liubenoff |
|
472 |
9 |
liubenoff |
Name Type Name Dir Delay Time Fan Out(s)
|
473 |
|
|
-------------------------------------------------------------------------------------------
|
474 |
6 |
liubenoff |
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
|
475 |
9 |
liubenoff |
symbol_scan_cntr[2] Net - - - - 15
|
476 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
477 |
5 |
liubenoff |
|
478 |
6 |
liubenoff |
symbol_scan_cntr_cry[2] Net - - - - 1
|
479 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
480 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
481 |
9 |
liubenoff |
symbol_scan_cntr_cry[4] Net - - - - 1
|
482 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
483 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
484 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
485 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
486 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
487 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
488 |
6 |
liubenoff |
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
489 |
9 |
liubenoff |
===========================================================================================
|
490 |
|
|
|
491 |
6 |
liubenoff |
|
492 |
9 |
liubenoff |
Path information for path number 4:
|
493 |
|
|
Requested Period: 2.305
|
494 |
6 |
liubenoff |
- Setup time: 0.211
|
495 |
9 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
496 |
|
|
= Required time: 2.094
|
497 |
6 |
liubenoff |
|
498 |
9 |
liubenoff |
- Propagation time: 2.442
|
499 |
6 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
500 |
5 |
liubenoff |
|
501 |
|
|
|
502 |
|
|
Number of logic level(s): 4
|
503 |
9 |
liubenoff |
Starting point: symbol_scan_cntr[0] / Q
|
504 |
5 |
liubenoff |
Ending point: symbol_scan_cntr[5] / D
|
505 |
|
|
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
506 |
9 |
liubenoff |
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
507 |
5 |
liubenoff |
|
508 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
509 |
5 |
liubenoff |
Name Type Name Dir Delay Time Fan Out(s)
|
510 |
9 |
liubenoff |
-------------------------------------------------------------------------------------------
|
511 |
5 |
liubenoff |
|
512 |
6 |
liubenoff |
symbol_scan_cntr[0] Net - - - - 15
|
513 |
9 |
liubenoff |
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
514 |
6 |
liubenoff |
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
515 |
9 |
liubenoff |
symbol_scan_cntr_cry[0] Net - - - - 1
|
516 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
517 |
5 |
liubenoff |
|
518 |
6 |
liubenoff |
symbol_scan_cntr_cry[2] Net - - - - 1
|
519 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
520 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
521 |
9 |
liubenoff |
symbol_scan_cntr_cry[4] Net - - - - 1
|
522 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
523 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
|
524 |
6 |
liubenoff |
symbol_scan_cntr_s[5] Net - - - - 1
|
525 |
|
|
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
|
526 |
|
|
===========================================================================================
|
527 |
|
|
|
528 |
|
|
|
529 |
|
|
Path information for path number 5:
|
530 |
|
|
Requested Period: 2.305
|
531 |
|
|
- Setup time: 0.211
|
532 |
|
|
+ Clock delay at ending point: 0.000 (ideal)
|
533 |
|
|
= Required time: 2.094
|
534 |
|
|
|
535 |
9 |
liubenoff |
- Propagation time: 2.442
|
536 |
6 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
537 |
5 |
liubenoff |
|
538 |
|
|
|
539 |
|
|
Number of logic level(s): 4
|
540 |
9 |
liubenoff |
Starting point: symbol_scan_cntr[0] / Q
|
541 |
5 |
liubenoff |
Ending point: symbol_scan_cntr[6] / D
|
542 |
|
|
The start point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
543 |
9 |
liubenoff |
The end point is clocked by display_driver_wrapper|clk [rising] on pin CK
|
544 |
5 |
liubenoff |
|
545 |
9 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
546 |
5 |
liubenoff |
Name Type Name Dir Delay Time Fan Out(s)
|
547 |
9 |
liubenoff |
-------------------------------------------------------------------------------------------
|
548 |
5 |
liubenoff |
|
549 |
9 |
liubenoff |
symbol_scan_cntr[0] Net - - - - 15
|
550 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
551 |
6 |
liubenoff |
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
552 |
9 |
liubenoff |
symbol_scan_cntr_cry[0] Net - - - - 1
|
553 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
554 |
5 |
liubenoff |
|
555 |
6 |
liubenoff |
symbol_scan_cntr_cry[2] Net - - - - 1
|
556 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
557 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
558 |
9 |
liubenoff |
symbol_scan_cntr_cry[4] Net - - - - 1
|
559 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
560 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
|
561 |
|
|
symbol_scan_cntr_s[6] Net - - - - 1
|
562 |
|
|
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
|
563 |
|
|
===========================================================================================
|
564 |
|
|
|
565 |
6 |
liubenoff |
|
566 |
9 |
liubenoff |
|
567 |
|
|
##### END OF TIMING REPORT #####]
|
568 |
6 |
liubenoff |
|
569 |
9 |
liubenoff |
Constraints that could not be applied
|
570 |
|
|
None
|
571 |
6 |
liubenoff |
|
572 |
9 |
liubenoff |
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
573 |
6 |
liubenoff |
|
574 |
5 |
liubenoff |
|
575 |
|
|
|
576 |
|
|
|
577 |
9 |
liubenoff |
---------------------------------------
|
578 |
5 |
liubenoff |
Resource Usage Report
|
579 |
|
|
Part: lfe5um5g_45f-8
|
580 |
9 |
liubenoff |
|
581 |
5 |
liubenoff |
|
582 |
9 |
liubenoff |
PIC Latch: 0
|
583 |
5 |
liubenoff |
I/O cells: 18
|
584 |
9 |
liubenoff |
|
585 |
5 |
liubenoff |
|
586 |
9 |
liubenoff |
Details:
|
587 |
|
|
CCU2C: 5
|
588 |
|
|
FD1P3DX: 8
|
589 |
|
|
FD1S3AX: 1
|
590 |
|
|
FD1S3JX: 3
|
591 |
5 |
liubenoff |
|
592 |
6 |
liubenoff |
IB: 3
|
593 |
|
|
IFS1P3JX: 1
|
594 |
|
|
INV: 2
|
595 |
9 |
liubenoff |
OB: 15
|
596 |
|
|
ORCALUT4: 4
|
597 |
|
|
PUR: 1
|
598 |
|
|
ROM128X1A: 14
|
599 |
|
|
VHI: 1
|
600 |
|
|
VLO: 1
|
601 |
|
|
Mapper successful!
|
602 |
|
|
|
603 |
|
|
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
604 |
|
|
|
605 |
6 |
liubenoff |
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
606 |
9 |
liubenoff |
# Wed Jan 18 01:08:17 2017
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