URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_synplify.lpf] - Blame information for rev 9

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#
# Logical Preferences generated for Lattice by Synplify maplat, Build 1498R.
#
 
# Period Constraints
#FREQUENCY PORT "clk" 433.9 MHz;
 
 
# Output Constraints
 
# Input Constraints
 
# Point-to-point Delay Constraints
 
 
 
# Block Path Constraints
 
BLOCK ASYNCPATHS;
 
# End of generated Logical Preferences.

Line No.	Rev	Author	Line
1	5	liubenoff	`#`
2			`# Logical Preferences generated for Lattice by Synplify maplat, Build 1498R.`
3			`#`
4
5			`# Period Constraints`
6	9	liubenoff	`#FREQUENCY PORT "clk" 433.9 MHz;`
7	5	liubenoff
8
9			`# Output Constraints`
10
11			`# Input Constraints`
12
13			`# Point-to-point Delay Constraints`
14
15
16
17			`# Block Path Constraints`
18
19			`BLOCK ASYNCPATHS;`
20
21			`# End of generated Logical Preferences.`

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [DisplayDriverwDecoder_impl1_synplify.lpf] - Blame information for rev 9