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<HEAD><TITLE>Lattice Map TRACE Report</TITLE>
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</HEAD>
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<PRE><A name="Map_Twr"></A><B><U><big>Map TRACE Report</big></U></B>
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Loading design for application trce from file displaydriverwdecoder_impl1_map.ncd.
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Design name: display_driver_wrapper
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NCD version: 3.3
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Vendor: LATTICE
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Device: LFE5UM5G-45F
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Package: CABGA381
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Performance: 8
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Loading device for application trce from file 'sa5p45m.nph' in environment: C:/lscc/diamond/3.8_x64/ispfpga.
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Package Status: Final Version 1.36.
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Performance Hardware Data Status: Final Version 50.1.
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Setup and Hold Report
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--------------------------------------------------------------------------------
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<A name="Map_Twr_setup"></A><B><U><big>Lattice TRACE Report - Setup, Version Diamond (64-bit) 3.8.0.115.3</big></U></B>
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Wed Jan 18 01:08:27 2017
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Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
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Copyright (c) 1995 AT&T Corp. All rights reserved.
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
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<A name="mtw1_set_ri"></A><B><U><big>Report Information</big></U></B>
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------------------
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf
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Design file: displaydriverwdecoder_impl1_map.ncd
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Preference file: displaydriverwdecoder_impl1.prf
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Device,speed: LFE5UM5G-45F,8
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Report level: verbose report, limited to 1 item per preference
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--------------------------------------------------------------------------------
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<A name="mtw1_set_ps"></A><B><U><big>Preference Summary</big></U></B>
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<LI><A href='#map_twr_pref_0_0' Target='right'>FREQUENCY NET "clk_c" 369.959000 MHz (0 errors)</A></LI> 68 items scored, 0 timing errors detected.
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Report: 370.096MHz is the maximum frequency for this preference.
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Report Type: based on TRACE automatically generated preferences
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BLOCK ASYNCPATHS
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BLOCK RESETPATHS
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--------------------------------------------------------------------------------
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================================================================================
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<A name="map_twr_pref_0_0"></A>Preference: FREQUENCY NET "clk_c" 369.959000 MHz ;
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68 items scored, 0 timing errors detected.
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--------------------------------------------------------------------------------
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Passed: The following path meets requirements by 0.001ns
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The internal maximum frequency of the following component is 370.096 MHz
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Logical Details: Cell type Pin name Component name
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Destination: SIOLOGIC CLK button_MGIOL
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Passed: The following path meets requirements by 1.063ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q bttn_state (from clk_c +)
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Destination: FF Data in symbol_scan_cntr[7] (to clk_c +)
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Delay: 1.749ns (43.2% logic, 56.8% route), 3 logic levels.
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Constraint Details:
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1.749ns physical path delay SLICE_7 to SLICE_0 meets
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2.703ns delay constraint less
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-0.109ns CE_SET requirement (totaling 2.812ns) by 1.063ns
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Physical Path Details:
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Data path SLICE_7 to SLICE_0:
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REG_DEL --- 0.395 SLICE_7.CLK to SLICE_7.Q0 SLICE_7 (from clk_c)
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ROUTE 1 e 0.419 SLICE_7.Q0 to SLICE_64.B1 bttn_state_i
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CTOF_DEL --- 0.180 SLICE_64.B1 to SLICE_64.F1 SLICE_64
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ROUTE 1 e 0.156 SLICE_64.F1 to SLICE_64.A0 G_15_1
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ROUTE 5 e 0.419 SLICE_64.F0 to SLICE_0.CE bttn_state_fifo_0io_RNIB9K02[0] (to clk_c)
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--------
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1.749 (43.2% logic, 56.8% route), 3 logic levels.
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Report: 370.096MHz is the maximum frequency for this preference.
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<A name="mtw1_set_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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Preference | Constraint| Actual|Levels
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----------------------------------------------------------------------------
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FREQUENCY NET "clk_c" 369.959000 MHz ; | 369.959 MHz| 370.096 MHz| 0
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----------------------------------------------------------------------------
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All preferences were met.
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<A name="mtw1_set_clkda"></A><B><U><big>Clock Domains Analysis</big></U></B>
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Found 1 clocks:
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Clock Domain: clk_c Source: clk.PAD Loads: 9
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Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;
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<A name="mtw1_set_ts"></A><B><U><big>Timing summary (Setup):</big></U></B>
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Cumulative negative slack: 0
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--------------------------------------------------------------------------------
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<A name="Map_Twr_hold"></A><B><U><big>Lattice TRACE Report - Hold, Version Diamond (64-bit) 3.8.0.115.3</big></U></B>
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Wed Jan 18 01:08:28 2017
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Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
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Copyright (c) 2001 Agere Systems All rights reserved.
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Copyright (c) 2002-2016 Lattice Semiconductor Corporation, All rights reserved.
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Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o DisplayDriverwDecoder_impl1.tw1 -gui -msgset C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/promote.xml DisplayDriverwDecoder_impl1_map.ncd DisplayDriverwDecoder_impl1.prf
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Design file: displaydriverwdecoder_impl1_map.ncd
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Device,speed: LFE5UM5G-45F,M
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--------------------------------------------------------------------------------
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<A name="mtw1_hold_ps"></A><B><U><big>Preference Summary</big></U></B>
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BLOCK RESETPATHS
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================================================================================
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68 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 0.104ns
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Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
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Source: FF Q bttn_state_fifo[1] (from clk_c +)
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Delay: 0.222ns (73.9% logic, 26.1% route), 1 logic levels.
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Constraint Details:
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0.222ns physical path delay SLICE_5 to SLICE_5 meets
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0.118ns M_HLD and
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0.000ns delay constraint requirement (totaling 0.118ns) by 0.104ns
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Name Fanout Delay (ns) Site Resource
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REG_DEL --- 0.164 SLICE_5.CLK to SLICE_5.Q0 SLICE_5 (from clk_c)
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ROUTE 3 e 0.058 SLICE_5.Q0 to SLICE_5.M1 bttn_state_fifo[1] (to clk_c)
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--------
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0.222 (73.9% logic, 26.1% route), 1 logic levels.
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<A name="mtw1_hold_rs"></A><B><U><big>Report Summary</big></U></B>
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--------------
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----------------------------------------------------------------------------
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----------------------------------------------------------------------------
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Found 1 clocks:
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Clock Domain: clk_c Source: clk.PAD Loads: 9
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Covered under: FREQUENCY NET "clk_c" 369.959000 MHz ;
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---------------
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Timing errors: 0 Score: 0
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Constraints cover 68 paths, 1 nets, and 50 connections (7.61% coverage)
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---------------
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Timing errors: 0 (setup), 0 (hold)
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Score: 0 (setup), 0 (hold)
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Cumulative negative slack: 0 (0+0)
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