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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [impl1.srr] - Blame information for rev 5

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1 5 liubenoff 
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul  4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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# Sun Jan 08 00:49:32 2017
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#Implementation: impl1
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10 
Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
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@N|Running in 64-bit mode
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
13 
 
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Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul  5 2016
15 
@N|Running in 64-bit mode
16 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
17 
 
18 
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
19 
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
20 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
21 
VHDL syntax check successful!
22 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
23 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
24 
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
25 
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
26 
Post processing for work.displaydriverwdecoder_top.arch
27 
@W: CL240 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":38:8:38:16|disp_data is not assigned a value (floating) -- simulation mismatch possible.
28 
Post processing for work.displaydriverwrapper.arch
29 
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":20:8:20:13|Input button is unused.
30 
 
31 
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 70MB peak: 71MB)
32 
 
33 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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35 
Process completed successfully.
36 
# Sun Jan 08 00:49:32 2017
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38 
###########################################################]
39 
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
40 
@N|Running in 64-bit mode
41 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
42 
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
43 
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
44 
 
45 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
46 
 
47 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
48 
 
49 
Process completed successfully.
50 
# Sun Jan 08 00:49:32 2017
51 
 
52 
###########################################################]
53 
@END
54 
 
55 
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
56 
 
57 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
58 
 
59 
Process completed successfully.
60 
# Sun Jan 08 00:49:32 2017
61 
 
62 
###########################################################]
63 
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul  5 2016
64 
@N|Running in 64-bit mode
65 
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling
66 
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
67 
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
68 
 
69 
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
70 
 
71 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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73 
Process completed successfully.
74 
# Sun Jan 08 00:49:34 2017
75 
 
76 
###########################################################]
77 
Pre-mapping Report
78 
 
79 
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
80 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
81 
Product Version L-2016.03L-1
82 
 
83 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
84 
 
85 
@A: MF827 |No constraint file specified.
86 
@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt
87 
Printing clock  summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file
88 
@N: MF248 |Running in 64-bit mode.
89 
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
90 
 
91 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
92 
 
93 
 
94 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
95 
 
96 
 
97 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 112MB)
98 
 
99 
 
100 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 114MB)
101 
 
102 
ICG Latch Removal Summary:
103 
Number of ICG latches removed:  0
104 
Number of ICG latches not removed:      0
105 
syn_allowed_resources : blockrams=108  set on top level netlist DisplayDriverWrapper
106 
 
107 
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
108 
 
109 
 
110 
 
111 
Clock Summary
112 
*****************
113 
 
114 
Start                        Requested     Requested     Clock        Clock                     Clock
115 
Clock                        Frequency     Period        Type         Group                     Load
116 
-----------------------------------------------------------------------------------------------------
117 
DisplayDriverWrapper|clk     1.0 MHz       1000.000      inferred     Autoconstr_clkgroup_0     8
118 
=====================================================================================================
119 
 
120 
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":75:4:75:5|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
121 
 
122 
Finished Pre Mapping Phase.
123 
 
124 
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
125 
 
126 
None
127 
None
128 
 
129 
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
130 
 
131 
Pre-mapping successful!
132 
 
133 
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 141MB)
134 
 
135 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
136 
# Sun Jan 08 00:49:34 2017
137 
 
138 
###########################################################]
139 
Map & Optimize Report
140 
 
141 
Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul  5 2016 10:30:31
142 
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
143 
Product Version L-2016.03L-1
144 
 
145 
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
146 
 
147 
@N: MF248 |Running in 64-bit mode.
148 
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
149 
 
150 
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
151 
 
152 
 
153 
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
154 
 
155 
 
156 
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
157 
 
158 
 
159 
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
160 
 
161 
 
162 
 
163 
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
164 
 
165 
 
166 
Available hyper_sources - for debug and ip models
167 
        None Found
168 
 
169 
@N: MT206 |Auto Constrain mode is enabled
170 
 
171 
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
172 
 
173 
 
174 
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
175 
 
176 
 
177 
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
178 
 
179 
 
180 
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
181 
 
182 
 
183 
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
184 
 
185 
 
186 
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
187 
 
188 
 
189 
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
190 
 
191 
 
192 
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
193 
 
194 
 
195 
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
196 
 
197 
 
198 
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
199 
 
200 
Pass             CPU time               Worst Slack             Luts / Registers
201 
------------------------------------------------------------
202 
 
203 
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
204 
 
205 
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
206 
 
207 
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
208 
 
209 
 
210 
 
211 
@S |Clock Optimization Summary
212 
 
213 
 
214 
#### START OF CLOCK OPTIMIZATION REPORT #####[
215 
 
216 
1 non-gated/non-generated clock tree(s) driving 8 clock pin(s) of sequential element(s)
217 
 
218 
 
219 
 
220 
============================== Non-Gated/Non-Generated Clocks ===============================
221 
Clock Tree ID     Driving Element     Drive Element Type     Fanout     Sample Instance
222 
---------------------------------------------------------------------------------------------
223 
@K:CKID0001       clk                 port                   8          DDwD_Top.ascii_reg[6]
224 
=============================================================================================
225 
 
226 
 
227 
##### END OF CLOCK OPTIMIZATION REPORT ######]
228 
 
229 
 
230 
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
231 
 
232 
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
233 
 
234 
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 138MB peak: 141MB)
235 
 
236 
Writing EDIF Netlist and constraint files
237 
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
238 
L-2016.03L-1
239 
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
240 
 
241 
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 142MB peak: 144MB)
242 
 
243 
 
244 
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
245 
 
246 
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.77ns. Please declare a user-defined clock on object "p:clk"
247 
 
248 
 
249 
##### START OF TIMING REPORT #####[
250 
# Timing Report written on Sun Jan 08 00:49:36 2017
251 
#
252 
 
253 
 
254 
Top view:               DisplayDriverWrapper
255 
Requested Frequency:    1297.0 MHz
256 
Wire load mode:         top
257 
Paths requested:        5
258 
Constraint File(s):
259 
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
260 
 
261 
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
262 
 
263 
 
264 
 
265 
Performance Summary
266 
*******************
267 
 
268 
 
269 
Worst slack in design: -0.136
270 
 
271 
                             Requested      Estimated      Requested     Estimated                Clock        Clock
272 
Starting Clock               Frequency      Frequency      Period        Period        Slack      Type         Group
273 
------------------------------------------------------------------------------------------------------------------------------------
274 
DisplayDriverWrapper|clk     1297.0 MHz     1102.5 MHz     0.771         0.907         -0.136     inferred     Autoconstr_clkgroup_0
275 
====================================================================================================================================
276 
 
277 
 
278 
 
279 
 
280 
 
281 
Clock Relationships
282 
*******************
283 
 
284 
Clocks                                              |    rise  to  rise    |    fall  to  fall   |    rise  to  fall   |    fall  to  rise
285 
-------------------------------------------------------------------------------------------------------------------------------------------
286 
Starting                  Ending                    |  constraint  slack   |  constraint  slack  |  constraint  slack  |  constraint  slack
287 
-------------------------------------------------------------------------------------------------------------------------------------------
288 
DisplayDriverWrapper|clk  DisplayDriverWrapper|clk  |  0.771       -0.136  |  No paths    -      |  No paths    -      |  No paths    -
289 
===========================================================================================================================================
290 
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
291 
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
292 
 
293 
 
294 
 
295 
Interface Information
296 
*********************
297 
 
298 
No IO constraint found
299 
 
300 
 
301 
 
302 
====================================
303 
Detailed Report for Clock: DisplayDriverWrapper|clk
304 
====================================
305 
 
306 
 
307 
 
308 
Starting Points with Worst Slack
309 
********************************
310 
 
311 
                          Starting                                                          Arrival
312 
Instance                  Reference                    Type        Pin     Net              Time        Slack
313 
                          Clock
314 
--------------------------------------------------------------------------------------------------------------
315 
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[0]     0.853       -0.136
316 
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[1]     0.853       -0.136
317 
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[2]     0.853       -0.136
318 
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[3]     0.853       -0.136
319 
DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[4]     0.853       -0.136
320 
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[5]     0.853       -0.136
321 
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     Q       ascii_reg[6]     0.853       -0.136
322 
DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     Q       ascii_reg[7]     0.853       -0.136
323 
==============================================================================================================
324 
 
325 
 
326 
Ending Points with Worst Slack
327 
******************************
328 
 
329 
                          Starting                                                          Required
330 
Instance                  Reference                    Type        Pin     Net              Time         Slack
331 
                          Clock
332 
---------------------------------------------------------------------------------------------------------------
333 
DDwD_Top.ascii_reg[0]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[0]     0.717        -0.136
334 
DDwD_Top.ascii_reg[1]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[1]     0.717        -0.136
335 
DDwD_Top.ascii_reg[2]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[2]     0.717        -0.136
336 
DDwD_Top.ascii_reg[3]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[3]     0.717        -0.136
337 
DDwD_Top.ascii_reg[4]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[4]     0.717        -0.136
338 
DDwD_Top.ascii_reg[5]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[5]     0.717        -0.136
339 
DDwD_Top.ascii_reg[6]     DisplayDriverWrapper|clk     FD1S3JX     D       ascii_reg[6]     0.717        -0.136
340 
DDwD_Top.ascii_reg[7]     DisplayDriverWrapper|clk     FD1S3IX     D       ascii_reg[7]     0.717        -0.136
341 
===============================================================================================================
342 
 
343 
 
344 
 
345 
Worst Path Information
346 
***********************
347 
 
348 
 
349 
Path information for path number 1:
350 
      Requested Period:                      0.771
351 
    - Setup time:                            0.054
352 
    + Clock delay at ending point:           0.000 (ideal)
353 
    = Required time:                         0.717
354 
 
355 
    - Propagation time:                      0.853
356 
    - Clock delay at starting point:         0.000 (ideal)
357 
    = Slack (critical) :                     -0.136
358 
 
359 
    Number of logic level(s):                0
360 
    Starting point:                          DDwD_Top.ascii_reg[0] / Q
361 
    Ending point:                            DDwD_Top.ascii_reg[0] / D
362 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
363 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
364 
 
365 
Instance / Net                        Pin      Pin               Arrival     No. of
366 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
367 
---------------------------------------------------------------------------------------
368 
DDwD_Top.ascii_reg[0]     FD1S3IX     Q        Out     0.853     0.853       -
369 
ascii_reg[0]              Net         -        -       -         -           1
370 
DDwD_Top.ascii_reg[0]     FD1S3IX     D        In      0.000     0.853       -
371 
=======================================================================================
372 
 
373 
 
374 
Path information for path number 2:
375 
      Requested Period:                      0.771
376 
    - Setup time:                            0.054
377 
    + Clock delay at ending point:           0.000 (ideal)
378 
    = Required time:                         0.717
379 
 
380 
    - Propagation time:                      0.853
381 
    - Clock delay at starting point:         0.000 (ideal)
382 
    = Slack (critical) :                     -0.136
383 
 
384 
    Number of logic level(s):                0
385 
    Starting point:                          DDwD_Top.ascii_reg[1] / Q
386 
    Ending point:                            DDwD_Top.ascii_reg[1] / D
387 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
388 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
389 
 
390 
Instance / Net                        Pin      Pin               Arrival     No. of
391 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
392 
---------------------------------------------------------------------------------------
393 
DDwD_Top.ascii_reg[1]     FD1S3JX     Q        Out     0.853     0.853       -
394 
ascii_reg[1]              Net         -        -       -         -           1
395 
DDwD_Top.ascii_reg[1]     FD1S3JX     D        In      0.000     0.853       -
396 
=======================================================================================
397 
 
398 
 
399 
Path information for path number 3:
400 
      Requested Period:                      0.771
401 
    - Setup time:                            0.054
402 
    + Clock delay at ending point:           0.000 (ideal)
403 
    = Required time:                         0.717
404 
 
405 
    - Propagation time:                      0.853
406 
    - Clock delay at starting point:         0.000 (ideal)
407 
    = Slack (critical) :                     -0.136
408 
 
409 
    Number of logic level(s):                0
410 
    Starting point:                          DDwD_Top.ascii_reg[2] / Q
411 
    Ending point:                            DDwD_Top.ascii_reg[2] / D
412 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
413 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
414 
 
415 
Instance / Net                        Pin      Pin               Arrival     No. of
416 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
417 
---------------------------------------------------------------------------------------
418 
DDwD_Top.ascii_reg[2]     FD1S3IX     Q        Out     0.853     0.853       -
419 
ascii_reg[2]              Net         -        -       -         -           1
420 
DDwD_Top.ascii_reg[2]     FD1S3IX     D        In      0.000     0.853       -
421 
=======================================================================================
422 
 
423 
 
424 
Path information for path number 4:
425 
      Requested Period:                      0.771
426 
    - Setup time:                            0.054
427 
    + Clock delay at ending point:           0.000 (ideal)
428 
    = Required time:                         0.717
429 
 
430 
    - Propagation time:                      0.853
431 
    - Clock delay at starting point:         0.000 (ideal)
432 
    = Slack (critical) :                     -0.136
433 
 
434 
    Number of logic level(s):                0
435 
    Starting point:                          DDwD_Top.ascii_reg[3] / Q
436 
    Ending point:                            DDwD_Top.ascii_reg[3] / D
437 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
438 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
439 
 
440 
Instance / Net                        Pin      Pin               Arrival     No. of
441 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
442 
---------------------------------------------------------------------------------------
443 
DDwD_Top.ascii_reg[3]     FD1S3IX     Q        Out     0.853     0.853       -
444 
ascii_reg[3]              Net         -        -       -         -           1
445 
DDwD_Top.ascii_reg[3]     FD1S3IX     D        In      0.000     0.853       -
446 
=======================================================================================
447 
 
448 
 
449 
Path information for path number 5:
450 
      Requested Period:                      0.771
451 
    - Setup time:                            0.054
452 
    + Clock delay at ending point:           0.000 (ideal)
453 
    = Required time:                         0.717
454 
 
455 
    - Propagation time:                      0.853
456 
    - Clock delay at starting point:         0.000 (ideal)
457 
    = Slack (critical) :                     -0.136
458 
 
459 
    Number of logic level(s):                0
460 
    Starting point:                          DDwD_Top.ascii_reg[4] / Q
461 
    Ending point:                            DDwD_Top.ascii_reg[4] / D
462 
    The start point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
463 
    The end   point is clocked by            DisplayDriverWrapper|clk [rising] on pin CK
464 
 
465 
Instance / Net                        Pin      Pin               Arrival     No. of
466 
Name                      Type        Name     Dir     Delay     Time        Fan Out(s)
467 
---------------------------------------------------------------------------------------
468 
DDwD_Top.ascii_reg[4]     FD1S3JX     Q        Out     0.853     0.853       -
469 
ascii_reg[4]              Net         -        -       -         -           1
470 
DDwD_Top.ascii_reg[4]     FD1S3JX     D        In      0.000     0.853       -
471 
=======================================================================================
472 
 
473 
 
474 
 
475 
##### END OF TIMING REPORT #####]
476 
 
477 
Constraints that could not be applied
478 
None
479 
 
480 
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
481 
 
482 
 
483 
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 144MB)
484 
 
485 
---------------------------------------
486 
Resource Usage Report
487 
Part: lfe5u_45f-6
488 
 
489 
Register bits: 8 of 43848 (0%)
490 
PIC Latch:       0
491 
I/O cells:       17
492 
 
493 
 
494 
Details:
495 
FD1S3IX:        5
496 
FD1S3JX:        3
497 
GSR:            1
498 
IB:             2
499 
OB:             15
500 
PUR:            1
501 
VHI:            2
502 
VLO:            1
503 
false:          1
504 
Mapper successful!
505 
 
506 
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 144MB)
507 
 
508 
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
509 
# Sun Jan 08 00:49:36 2017
510 
 
511 
###########################################################]

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