| 1 |
5 |
liubenoff |
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
|
| 2 |
|
|
#install: C:\lscc\diamond\3.8_x64\synpbase
|
| 3 |
|
|
#OS: Windows 8 6.2
|
| 4 |
|
|
#Hostname: DESKTOP-1AUKF7V
|
| 5 |
|
|
|
| 6 |
6 |
liubenoff |
# Tue Jan 17 01:29:36 2017
|
| 7 |
5 |
liubenoff |
|
| 8 |
|
|
#Implementation: impl1
|
| 9 |
|
|
|
| 10 |
|
|
Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
|
| 11 |
|
|
@N|Running in 64-bit mode
|
| 12 |
|
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
| 13 |
|
|
|
| 14 |
|
|
Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
|
| 15 |
|
|
@N|Running in 64-bit mode
|
| 16 |
|
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
| 17 |
|
|
|
| 18 |
|
|
@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
|
| 19 |
|
|
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
|
| 20 |
6 |
liubenoff |
Options changed - recompiling
|
| 21 |
5 |
liubenoff |
VHDL syntax check successful!
|
| 22 |
|
|
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
|
| 23 |
|
|
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":16:7:16:31|Synthesizing work.displaydriverwdecoder_top.arch.
|
| 24 |
6 |
liubenoff |
@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":53:11:53:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
|
| 25 |
|
|
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
|
| 26 |
|
|
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
|
| 27 |
|
|
@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
|
| 28 |
|
|
Post processing for work.rom128x1a.syn_black_box
|
| 29 |
|
|
Post processing for work.distromasciidecoder.structure
|
| 30 |
|
|
Post processing for work.asciidecoder.arch
|
| 31 |
5 |
liubenoff |
Post processing for work.displaydriverwdecoder_top.arch
|
| 32 |
|
|
Post processing for work.displaydriverwrapper.arch
|
| 33 |
6 |
liubenoff |
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":17:8:17:10|Input clk is unused.
|
| 34 |
|
|
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd":18:8:18:12|Input reset is unused.
|
| 35 |
|
|
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd":29:8:29:12|Input wr_en is unused.
|
| 36 |
5 |
liubenoff |
|
| 37 |
6 |
liubenoff |
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
|
| 38 |
5 |
liubenoff |
|
| 39 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 40 |
|
|
|
| 41 |
|
|
Process completed successfully.
|
| 42 |
6 |
liubenoff |
# Tue Jan 17 01:29:36 2017
|
| 43 |
5 |
liubenoff |
|
| 44 |
|
|
###########################################################]
|
| 45 |
|
|
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
|
| 46 |
|
|
@N|Running in 64-bit mode
|
| 47 |
|
|
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
|
| 48 |
|
|
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
|
| 49 |
|
|
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
|
| 50 |
|
|
|
| 51 |
|
|
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
| 52 |
|
|
|
| 53 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 54 |
|
|
|
| 55 |
|
|
Process completed successfully.
|
| 56 |
6 |
liubenoff |
# Tue Jan 17 01:29:36 2017
|
| 57 |
5 |
liubenoff |
|
| 58 |
|
|
###########################################################]
|
| 59 |
|
|
@END
|
| 60 |
|
|
|
| 61 |
|
|
At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
|
| 62 |
|
|
|
| 63 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 64 |
|
|
|
| 65 |
|
|
Process completed successfully.
|
| 66 |
6 |
liubenoff |
# Tue Jan 17 01:29:36 2017
|
| 67 |
5 |
liubenoff |
|
| 68 |
|
|
###########################################################]
|
| 69 |
|
|
Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
|
| 70 |
|
|
@N|Running in 64-bit mode
|
| 71 |
|
|
File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling
|
| 72 |
|
|
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
|
| 73 |
|
|
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
|
| 74 |
|
|
|
| 75 |
|
|
At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
|
| 76 |
|
|
|
| 77 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 78 |
|
|
|
| 79 |
|
|
Process completed successfully.
|
| 80 |
6 |
liubenoff |
# Tue Jan 17 01:29:37 2017
|
| 81 |
5 |
liubenoff |
|
| 82 |
|
|
###########################################################]
|
| 83 |
|
|
Pre-mapping Report
|
| 84 |
|
|
|
| 85 |
|
|
Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
|
| 86 |
|
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
| 87 |
|
|
Product Version L-2016.03L-1
|
| 88 |
|
|
|
| 89 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
| 90 |
|
|
|
| 91 |
|
|
@A: MF827 |No constraint file specified.
|
| 92 |
|
|
@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt
|
| 93 |
|
|
Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file
|
| 94 |
|
|
@N: MF248 |Running in 64-bit mode.
|
| 95 |
|
|
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
| 96 |
|
|
|
| 97 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
| 98 |
|
|
|
| 99 |
|
|
|
| 100 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
| 101 |
|
|
|
| 102 |
|
|
|
| 103 |
6 |
liubenoff |
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
|
| 104 |
5 |
liubenoff |
|
| 105 |
|
|
|
| 106 |
6 |
liubenoff |
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
|
| 107 |
5 |
liubenoff |
|
| 108 |
|
|
ICG Latch Removal Summary:
|
| 109 |
|
|
Number of ICG latches removed: 0
|
| 110 |
|
|
Number of ICG latches not removed: 0
|
| 111 |
|
|
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
|
| 112 |
|
|
|
| 113 |
6 |
liubenoff |
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
| 114 |
5 |
liubenoff |
|
| 115 |
|
|
|
| 116 |
|
|
|
| 117 |
|
|
Clock Summary
|
| 118 |
|
|
*****************
|
| 119 |
|
|
|
| 120 |
6 |
liubenoff |
Start Requested Requested Clock Clock Clock
|
| 121 |
|
|
Clock Frequency Period Type Group Load
|
| 122 |
|
|
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
| 123 |
|
|
DisplayDriverWrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from DisplayDriverWrapper|clk) Autoconstr_clkgroup_0 8
|
| 124 |
|
|
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
|
| 125 |
|
|
=========================================================================================================================================================
|
| 126 |
5 |
liubenoff |
|
| 127 |
6 |
liubenoff |
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
| 128 |
5 |
liubenoff |
|
| 129 |
|
|
Finished Pre Mapping Phase.
|
| 130 |
|
|
|
| 131 |
6 |
liubenoff |
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
| 132 |
5 |
liubenoff |
|
| 133 |
|
|
None
|
| 134 |
|
|
None
|
| 135 |
|
|
|
| 136 |
6 |
liubenoff |
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
| 137 |
5 |
liubenoff |
|
| 138 |
|
|
Pre-mapping successful!
|
| 139 |
|
|
|
| 140 |
6 |
liubenoff |
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)
|
| 141 |
5 |
liubenoff |
|
| 142 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 143 |
6 |
liubenoff |
# Tue Jan 17 01:29:38 2017
|
| 144 |
5 |
liubenoff |
|
| 145 |
|
|
###########################################################]
|
| 146 |
|
|
Map & Optimize Report
|
| 147 |
|
|
|
| 148 |
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
|
| 149 |
|
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
| 150 |
|
|
Product Version L-2016.03L-1
|
| 151 |
|
|
|
| 152 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
| 153 |
|
|
|
| 154 |
|
|
@N: MF248 |Running in 64-bit mode.
|
| 155 |
|
|
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
| 156 |
|
|
|
| 157 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
| 158 |
|
|
|
| 159 |
|
|
|
| 160 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
| 161 |
|
|
|
| 162 |
|
|
|
| 163 |
|
|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
| 164 |
|
|
|
| 165 |
|
|
|
| 166 |
|
|
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
| 167 |
|
|
|
| 168 |
|
|
|
| 169 |
|
|
|
| 170 |
|
|
Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 171 |
|
|
|
| 172 |
|
|
|
| 173 |
|
|
Available hyper_sources - for debug and ip models
|
| 174 |
|
|
None Found
|
| 175 |
|
|
|
| 176 |
|
|
@N: MT206 |Auto Constrain mode is enabled
|
| 177 |
|
|
|
| 178 |
|
|
Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 179 |
|
|
|
| 180 |
6 |
liubenoff |
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
|
| 181 |
5 |
liubenoff |
|
| 182 |
|
|
Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 183 |
|
|
|
| 184 |
|
|
|
| 185 |
|
|
Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 186 |
|
|
|
| 187 |
|
|
|
| 188 |
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 189 |
|
|
|
| 190 |
|
|
|
| 191 |
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 192 |
|
|
|
| 193 |
|
|
|
| 194 |
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 195 |
|
|
|
| 196 |
|
|
|
| 197 |
6 |
liubenoff |
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
| 198 |
5 |
liubenoff |
|
| 199 |
|
|
|
| 200 |
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 201 |
|
|
|
| 202 |
|
|
|
| 203 |
|
|
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 204 |
|
|
|
| 205 |
|
|
|
| 206 |
|
|
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 207 |
|
|
|
| 208 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
| 209 |
|
|
------------------------------------------------------------
|
| 210 |
6 |
liubenoff |
1 0h:00m:00s -0.76ns 6 / 13
|
| 211 |
|
|
2 0h:00m:00s -0.76ns 6 / 13
|
| 212 |
5 |
liubenoff |
|
| 213 |
6 |
liubenoff |
3 0h:00m:00s -0.62ns 7 / 13
|
| 214 |
|
|
|
| 215 |
|
|
|
| 216 |
|
|
4 0h:00m:00s -0.58ns 6 / 13
|
| 217 |
|
|
|
| 218 |
5 |
liubenoff |
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 219 |
|
|
|
| 220 |
|
|
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
| 221 |
|
|
|
| 222 |
6 |
liubenoff |
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
| 223 |
5 |
liubenoff |
|
| 224 |
6 |
liubenoff |
@N: MT611 :|Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
|
| 225 |
5 |
liubenoff |
|
| 226 |
|
|
|
| 227 |
|
|
@S |Clock Optimization Summary
|
| 228 |
|
|
|
| 229 |
|
|
|
| 230 |
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
| 231 |
|
|
|
| 232 |
6 |
liubenoff |
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
|
| 233 |
5 |
liubenoff |
|
| 234 |
6 |
liubenoff |
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
| 235 |
5 |
liubenoff |
|
| 236 |
6 |
liubenoff |
=========================== Non-Gated/Non-Generated Clocks ============================
|
| 237 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
| 238 |
|
|
---------------------------------------------------------------------------------------
|
| 239 |
|
|
@K:CKID0001 clk port 13 bttn_state
|
| 240 |
|
|
=======================================================================================
|
| 241 |
5 |
liubenoff |
|
| 242 |
|
|
|
| 243 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
| 244 |
|
|
|
| 245 |
|
|
|
| 246 |
|
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
|
| 247 |
|
|
|
| 248 |
|
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
|
| 249 |
|
|
|
| 250 |
6 |
liubenoff |
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
| 251 |
5 |
liubenoff |
|
| 252 |
|
|
Writing EDIF Netlist and constraint files
|
| 253 |
|
|
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
|
| 254 |
|
|
L-2016.03L-1
|
| 255 |
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
| 256 |
|
|
|
| 257 |
6 |
liubenoff |
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 143MB peak: 145MB)
|
| 258 |
5 |
liubenoff |
|
| 259 |
|
|
|
| 260 |
6 |
liubenoff |
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
| 261 |
5 |
liubenoff |
|
| 262 |
6 |
liubenoff |
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
|
| 263 |
5 |
liubenoff |
|
| 264 |
|
|
|
| 265 |
|
|
##### START OF TIMING REPORT #####[
|
| 266 |
6 |
liubenoff |
# Timing Report written on Tue Jan 17 01:29:40 2017
|
| 267 |
5 |
liubenoff |
#
|
| 268 |
|
|
|
| 269 |
|
|
|
| 270 |
|
|
Top view: DisplayDriverWrapper
|
| 271 |
6 |
liubenoff |
Requested Frequency: 433.9 MHz
|
| 272 |
5 |
liubenoff |
Wire load mode: top
|
| 273 |
|
|
Paths requested: 5
|
| 274 |
|
|
Constraint File(s):
|
| 275 |
|
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
| 276 |
|
|
|
| 277 |
|
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
| 278 |
|
|
|
| 279 |
|
|
|
| 280 |
|
|
|
| 281 |
|
|
Performance Summary
|
| 282 |
|
|
*******************
|
| 283 |
|
|
|
| 284 |
|
|
|
| 285 |
6 |
liubenoff |
Worst slack in design: -0.407
|
| 286 |
5 |
liubenoff |
|
| 287 |
6 |
liubenoff |
Requested Estimated Requested Estimated Clock Clock
|
| 288 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
| 289 |
|
|
----------------------------------------------------------------------------------------------------------------------------------
|
| 290 |
|
|
DisplayDriverWrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
|
| 291 |
|
|
==================================================================================================================================
|
| 292 |
5 |
liubenoff |
|
| 293 |
|
|
|
| 294 |
|
|
|
| 295 |
|
|
|
| 296 |
|
|
|
| 297 |
|
|
Clock Relationships
|
| 298 |
|
|
*******************
|
| 299 |
|
|
|
| 300 |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
| 301 |
|
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
| 302 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
| 303 |
|
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
| 304 |
6 |
liubenoff |
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
|
| 305 |
5 |
liubenoff |
===========================================================================================================================================
|
| 306 |
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
| 307 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
| 308 |
|
|
|
| 309 |
|
|
|
| 310 |
|
|
|
| 311 |
|
|
Interface Information
|
| 312 |
|
|
*********************
|
| 313 |
|
|
|
| 314 |
|
|
No IO constraint found
|
| 315 |
|
|
|
| 316 |
|
|
|
| 317 |
|
|
|
| 318 |
|
|
====================================
|
| 319 |
|
|
Detailed Report for Clock: DisplayDriverWrapper|clk
|
| 320 |
|
|
====================================
|
| 321 |
|
|
|
| 322 |
|
|
|
| 323 |
|
|
|
| 324 |
|
|
Starting Points with Worst Slack
|
| 325 |
|
|
********************************
|
| 326 |
|
|
|
| 327 |
6 |
liubenoff |
Starting Arrival
|
| 328 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 329 |
|
|
Clock
|
| 330 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
| 331 |
|
|
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
|
| 332 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
|
| 333 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
|
| 334 |
|
|
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
|
| 335 |
|
|
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
|
| 336 |
|
|
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
|
| 337 |
|
|
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
|
| 338 |
|
|
bttn_state_fifo[3] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
|
| 339 |
|
|
bttn_state DisplayDriverWrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
|
| 340 |
|
|
bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
|
| 341 |
|
|
===================================================================================================================
|
| 342 |
5 |
liubenoff |
|
| 343 |
|
|
|
| 344 |
|
|
Ending Points with Worst Slack
|
| 345 |
|
|
******************************
|
| 346 |
|
|
|
| 347 |
6 |
liubenoff |
Starting Required
|
| 348 |
|
|
Instance Reference Type Pin Net Time Slack
|
| 349 |
|
|
Clock
|
| 350 |
|
|
--------------------------------------------------------------------------------------------------------------------------------
|
| 351 |
|
|
symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
|
| 352 |
|
|
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
|
| 353 |
|
|
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
|
| 354 |
|
|
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
|
| 355 |
|
|
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
|
| 356 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
|
| 357 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
|
| 358 |
|
|
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
| 359 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
| 360 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
| 361 |
|
|
================================================================================================================================
|
| 362 |
5 |
liubenoff |
|
| 363 |
|
|
|
| 364 |
|
|
|
| 365 |
|
|
Worst Path Information
|
| 366 |
|
|
***********************
|
| 367 |
|
|
|
| 368 |
|
|
|
| 369 |
|
|
Path information for path number 1:
|
| 370 |
6 |
liubenoff |
Requested Period: 2.305
|
| 371 |
|
|
- Setup time: 0.211
|
| 372 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 373 |
6 |
liubenoff |
= Required time: 2.094
|
| 374 |
5 |
liubenoff |
|
| 375 |
6 |
liubenoff |
- Propagation time: 2.501
|
| 376 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
| 377 |
6 |
liubenoff |
= Slack (critical) : -0.407
|
| 378 |
5 |
liubenoff |
|
| 379 |
6 |
liubenoff |
Number of logic level(s): 5
|
| 380 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
| 381 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
| 382 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 383 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 384 |
|
|
|
| 385 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 386 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 387 |
|
|
-------------------------------------------------------------------------------------------
|
| 388 |
|
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
| 389 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
| 390 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
| 391 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
| 392 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
| 393 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
| 394 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
| 395 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 396 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
| 397 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
| 398 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 399 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
| 400 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
|
| 401 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
| 402 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
|
| 403 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
|
| 404 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
| 405 |
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
|
| 406 |
|
|
===========================================================================================
|
| 407 |
5 |
liubenoff |
|
| 408 |
|
|
|
| 409 |
|
|
Path information for path number 2:
|
| 410 |
6 |
liubenoff |
Requested Period: 2.305
|
| 411 |
|
|
- Setup time: 0.211
|
| 412 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 413 |
6 |
liubenoff |
= Required time: 2.094
|
| 414 |
5 |
liubenoff |
|
| 415 |
6 |
liubenoff |
- Propagation time: 2.442
|
| 416 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
| 417 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
| 418 |
5 |
liubenoff |
|
| 419 |
6 |
liubenoff |
Number of logic level(s): 4
|
| 420 |
|
|
Starting point: symbol_scan_cntr[1] / Q
|
| 421 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
| 422 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 423 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 424 |
|
|
|
| 425 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 426 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 427 |
|
|
-------------------------------------------------------------------------------------------
|
| 428 |
|
|
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
|
| 429 |
|
|
symbol_scan_cntr[1] Net - - - - 15
|
| 430 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
| 431 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
| 432 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 433 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
| 434 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
| 435 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 436 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
| 437 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
| 438 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
| 439 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
| 440 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
| 441 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
| 442 |
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
| 443 |
|
|
===========================================================================================
|
| 444 |
5 |
liubenoff |
|
| 445 |
|
|
|
| 446 |
|
|
Path information for path number 3:
|
| 447 |
6 |
liubenoff |
Requested Period: 2.305
|
| 448 |
|
|
- Setup time: 0.211
|
| 449 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 450 |
6 |
liubenoff |
= Required time: 2.094
|
| 451 |
5 |
liubenoff |
|
| 452 |
6 |
liubenoff |
- Propagation time: 2.442
|
| 453 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
| 454 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
| 455 |
5 |
liubenoff |
|
| 456 |
6 |
liubenoff |
Number of logic level(s): 4
|
| 457 |
|
|
Starting point: symbol_scan_cntr[2] / Q
|
| 458 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
| 459 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 460 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 461 |
|
|
|
| 462 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 463 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 464 |
|
|
-------------------------------------------------------------------------------------------
|
| 465 |
|
|
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
|
| 466 |
|
|
symbol_scan_cntr[2] Net - - - - 15
|
| 467 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
| 468 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
| 469 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 470 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
| 471 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
| 472 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 473 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
| 474 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
| 475 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
| 476 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
| 477 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
| 478 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
| 479 |
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
| 480 |
|
|
===========================================================================================
|
| 481 |
5 |
liubenoff |
|
| 482 |
|
|
|
| 483 |
|
|
Path information for path number 4:
|
| 484 |
6 |
liubenoff |
Requested Period: 2.305
|
| 485 |
|
|
- Setup time: 0.211
|
| 486 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 487 |
6 |
liubenoff |
= Required time: 2.094
|
| 488 |
5 |
liubenoff |
|
| 489 |
6 |
liubenoff |
- Propagation time: 2.442
|
| 490 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
| 491 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
| 492 |
5 |
liubenoff |
|
| 493 |
6 |
liubenoff |
Number of logic level(s): 4
|
| 494 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
| 495 |
|
|
Ending point: symbol_scan_cntr[5] / D
|
| 496 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 497 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 498 |
|
|
|
| 499 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 500 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 501 |
|
|
-------------------------------------------------------------------------------------------
|
| 502 |
|
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
| 503 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
| 504 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
| 505 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
| 506 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
| 507 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
| 508 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
| 509 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 510 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
| 511 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
| 512 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 513 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
| 514 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
|
| 515 |
|
|
symbol_scan_cntr_s[5] Net - - - - 1
|
| 516 |
|
|
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
|
| 517 |
|
|
===========================================================================================
|
| 518 |
5 |
liubenoff |
|
| 519 |
|
|
|
| 520 |
|
|
Path information for path number 5:
|
| 521 |
6 |
liubenoff |
Requested Period: 2.305
|
| 522 |
|
|
- Setup time: 0.211
|
| 523 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
| 524 |
6 |
liubenoff |
= Required time: 2.094
|
| 525 |
5 |
liubenoff |
|
| 526 |
6 |
liubenoff |
- Propagation time: 2.442
|
| 527 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
| 528 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
| 529 |
5 |
liubenoff |
|
| 530 |
6 |
liubenoff |
Number of logic level(s): 4
|
| 531 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
| 532 |
|
|
Ending point: symbol_scan_cntr[6] / D
|
| 533 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 534 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
| 535 |
|
|
|
| 536 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
| 537 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
| 538 |
|
|
-------------------------------------------------------------------------------------------
|
| 539 |
|
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
| 540 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
| 541 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
| 542 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
| 543 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
| 544 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
| 545 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
| 546 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
| 547 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
| 548 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
| 549 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
| 550 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
| 551 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
|
| 552 |
|
|
symbol_scan_cntr_s[6] Net - - - - 1
|
| 553 |
|
|
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
|
| 554 |
|
|
===========================================================================================
|
| 555 |
5 |
liubenoff |
|
| 556 |
|
|
|
| 557 |
|
|
|
| 558 |
|
|
##### END OF TIMING REPORT #####]
|
| 559 |
|
|
|
| 560 |
|
|
Constraints that could not be applied
|
| 561 |
|
|
None
|
| 562 |
|
|
|
| 563 |
6 |
liubenoff |
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
| 564 |
5 |
liubenoff |
|
| 565 |
|
|
|
| 566 |
6 |
liubenoff |
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
| 567 |
5 |
liubenoff |
|
| 568 |
|
|
---------------------------------------
|
| 569 |
|
|
Resource Usage Report
|
| 570 |
6 |
liubenoff |
Part: lfe5um5g_45f-8
|
| 571 |
5 |
liubenoff |
|
| 572 |
6 |
liubenoff |
Register bits: 13 of 43848 (0%)
|
| 573 |
5 |
liubenoff |
PIC Latch: 0
|
| 574 |
6 |
liubenoff |
I/O cells: 19
|
| 575 |
5 |
liubenoff |
|
| 576 |
|
|
|
| 577 |
|
|
Details:
|
| 578 |
6 |
liubenoff |
CCU2C: 5
|
| 579 |
|
|
FD1P3DX: 8
|
| 580 |
|
|
FD1S3AX: 1
|
| 581 |
5 |
liubenoff |
FD1S3JX: 3
|
| 582 |
|
|
GSR: 1
|
| 583 |
6 |
liubenoff |
IB: 3
|
| 584 |
|
|
IFS1P3JX: 1
|
| 585 |
|
|
INV: 2
|
| 586 |
|
|
OB: 16
|
| 587 |
|
|
ORCALUT4: 4
|
| 588 |
5 |
liubenoff |
PUR: 1
|
| 589 |
6 |
liubenoff |
ROM128X1A: 14
|
| 590 |
|
|
VHI: 1
|
| 591 |
5 |
liubenoff |
VLO: 1
|
| 592 |
|
|
Mapper successful!
|
| 593 |
|
|
|
| 594 |
6 |
liubenoff |
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
| 595 |
5 |
liubenoff |
|
| 596 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
| 597 |
6 |
liubenoff |
# Tue Jan 17 01:29:40 2017
|
| 598 |
5 |
liubenoff |
|
| 599 |
|
|
###########################################################]
|
