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liubenoff |
#Build: Synplify Pro L-2016.03L-1, Build 097R, Jul 4 2016
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#install: C:\lscc\diamond\3.8_x64\synpbase
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#OS: Windows 8 6.2
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#Hostname: DESKTOP-1AUKF7V
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liubenoff |
# Tue Jan 17 23:41:19 2017
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liubenoff |
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#Implementation: impl1
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9 |
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10 |
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Synopsys HDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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@N|Running in 64-bit mode
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12 |
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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14 |
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Synopsys VHDL Compiler, version comp2016q2rc, Build 192R, built Jul 5 2016
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15 |
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@N|Running in 64-bit mode
|
16 |
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
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17 |
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@N: CD720 :"C:\lscc\diamond\3.8_x64\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
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19 |
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liubenoff |
@N:"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Top entity is set to DisplayDriverWrapper.
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20 |
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File C:\lscc\diamond\3.8_x64\synpbase\lib\lucent\ecp5um.vhd changed - recompiling
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21 |
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ASCIIDecoder.vhd changed - recompiling
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22 |
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverwDecoder_Top.vhd changed - recompiling
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23 |
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd changed - recompiling
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24 |
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liubenoff |
VHDL syntax check successful!
|
25 |
9 |
liubenoff |
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Synthesizing work.displaydriverwrapper.arch.
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26 |
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":17:7:17:30|Synthesizing work.display_driver_w_decoder.display_driver_w_decoder_arch.
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27 |
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@W: CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":47:11:47:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
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28 |
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@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":15:7:15:18|Synthesizing work.asciidecoder.arch.
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29 |
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liubenoff |
@N: CD630 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\Decoding_Table\ROM_ASCII_Decoder\DistRomAsciiDecoder\DistRomAsciiDecoder\DistRomAsciiDecoder.vhd":12:7:12:25|Synthesizing work.distromasciidecoder.structure.
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30 |
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@N: CD630 :"C:\lscc\diamond\3.8_x64\cae_library\synthesis\vhdl\ecp5um.vhd":801:10:801:18|Synthesizing work.rom128x1a.syn_black_box.
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31 |
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Post processing for work.rom128x1a.syn_black_box
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Post processing for work.distromasciidecoder.structure
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Post processing for work.asciidecoder.arch
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liubenoff |
Post processing for work.display_driver_w_decoder.display_driver_w_decoder_arch
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35 |
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liubenoff |
Post processing for work.displaydriverwrapper.arch
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36 |
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liubenoff |
@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":17:8:17:10|Input clk is unused.
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37 |
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\ascii_decoder.vhd":18:8:18:12|Input reset is unused.
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38 |
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@N: CL159 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":23:8:23:12|Input wr_en is unused.
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39 |
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liubenoff |
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liubenoff |
At c_vhdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 73MB peak: 74MB)
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liubenoff |
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
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Process completed successfully.
|
45 |
9 |
liubenoff |
# Tue Jan 17 23:41:20 2017
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5 |
liubenoff |
|
47 |
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###########################################################]
|
48 |
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
|
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@N|Running in 64-bit mode
|
50 |
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\layer0.srs changed - recompiling
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51 |
9 |
liubenoff |
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
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52 |
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@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
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53 |
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liubenoff |
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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55 |
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
57 |
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58 |
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Process completed successfully.
|
59 |
9 |
liubenoff |
# Tue Jan 17 23:41:20 2017
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60 |
5 |
liubenoff |
|
61 |
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###########################################################]
|
62 |
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@END
|
63 |
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|
64 |
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At c_hdl Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 3MB peak: 4MB)
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65 |
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66 |
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
67 |
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68 |
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Process completed successfully.
|
69 |
9 |
liubenoff |
# Tue Jan 17 23:41:20 2017
|
70 |
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liubenoff |
|
71 |
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###########################################################]
|
72 |
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Synopsys Netlist Linker, version comp2016q2rc, Build 192R, built Jul 5 2016
|
73 |
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@N|Running in 64-bit mode
|
74 |
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File C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_comp.srs changed - recompiling
|
75 |
9 |
liubenoff |
@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
|
76 |
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@N: NF107 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_wrapper.vhd":15:7:15:26|Selected library: work cell: DisplayDriverWrapper view arch as top level
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77 |
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liubenoff |
|
78 |
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At syn_nfilter Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 67MB peak: 68MB)
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80 |
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
81 |
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82 |
|
|
Process completed successfully.
|
83 |
9 |
liubenoff |
# Tue Jan 17 23:41:21 2017
|
84 |
5 |
liubenoff |
|
85 |
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###########################################################]
|
86 |
|
|
Pre-mapping Report
|
87 |
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|
88 |
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Synopsys Lattice Technology Pre-mapping, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
|
89 |
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Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
90 |
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Product Version L-2016.03L-1
|
91 |
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92 |
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Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
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93 |
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94 |
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@A: MF827 |No constraint file specified.
|
95 |
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@L: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt
|
96 |
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|
Printing clock summary report in "C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1_scck.rpt" file
|
97 |
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|
@N: MF248 |Running in 64-bit mode.
|
98 |
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@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
99 |
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100 |
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Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
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101 |
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102 |
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103 |
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Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 100MB peak: 102MB)
|
104 |
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105 |
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106 |
6 |
liubenoff |
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 113MB)
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107 |
5 |
liubenoff |
|
108 |
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109 |
6 |
liubenoff |
Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 112MB peak: 115MB)
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110 |
5 |
liubenoff |
|
111 |
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ICG Latch Removal Summary:
|
112 |
|
|
Number of ICG latches removed: 0
|
113 |
|
|
Number of ICG latches not removed: 0
|
114 |
|
|
syn_allowed_resources : blockrams=108 set on top level netlist DisplayDriverWrapper
|
115 |
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116 |
6 |
liubenoff |
Finished netlist restructuring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
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117 |
5 |
liubenoff |
|
118 |
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|
119 |
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|
120 |
|
|
Clock Summary
|
121 |
|
|
*****************
|
122 |
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123 |
6 |
liubenoff |
Start Requested Requested Clock Clock Clock
|
124 |
|
|
Clock Frequency Period Type Group Load
|
125 |
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|
---------------------------------------------------------------------------------------------------------------------------------------------------------
|
126 |
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|
DisplayDriverWrapper|bttn_state_derived_clock 1.0 MHz 1000.000 derived (from DisplayDriverWrapper|clk) Autoconstr_clkgroup_0 8
|
127 |
|
|
DisplayDriverWrapper|clk 1.0 MHz 1000.000 inferred Autoconstr_clkgroup_0 5
|
128 |
|
|
=========================================================================================================================================================
|
129 |
5 |
liubenoff |
|
130 |
9 |
liubenoff |
@W: MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":57:4:57:5|Found inferred clock DisplayDriverWrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
|
131 |
5 |
liubenoff |
|
132 |
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Finished Pre Mapping Phase.
|
133 |
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|
134 |
6 |
liubenoff |
Starting constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
135 |
5 |
liubenoff |
|
136 |
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None
|
137 |
|
|
None
|
138 |
|
|
|
139 |
6 |
liubenoff |
Finished constraint checker (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 142MB)
|
140 |
5 |
liubenoff |
|
141 |
|
|
Pre-mapping successful!
|
142 |
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|
143 |
6 |
liubenoff |
At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 55MB peak: 142MB)
|
144 |
5 |
liubenoff |
|
145 |
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Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
146 |
9 |
liubenoff |
# Tue Jan 17 23:41:22 2017
|
147 |
5 |
liubenoff |
|
148 |
|
|
###########################################################]
|
149 |
|
|
Map & Optimize Report
|
150 |
|
|
|
151 |
|
|
Synopsys Lattice Technology Mapper, Version maplat, Build 1498R, Built Jul 5 2016 10:30:31
|
152 |
|
|
Copyright (C) 1994-2016 Synopsys, Inc. All rights reserved. This Synopsys software and all associated documentation are proprietary to Synopsys, Inc. and may only be used pursuant to the terms and conditions of a written license agreement with Synopsys, Inc. All other use, reproduction, modification, or distribution of the Synopsys software or the associated documentation is strictly prohibited.
|
153 |
|
|
Product Version L-2016.03L-1
|
154 |
|
|
|
155 |
|
|
Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
156 |
|
|
|
157 |
|
|
@N: MF248 |Running in 64-bit mode.
|
158 |
|
|
@N: MF666 |Clock conversion enabled. (Command "set_option -fix_gated_and_generated_clocks 1" in the project file.)
|
159 |
|
|
|
160 |
|
|
Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
161 |
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|
162 |
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|
|
163 |
|
|
Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 99MB peak: 100MB)
|
164 |
|
|
|
165 |
|
|
|
166 |
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|
Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 112MB)
|
167 |
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|
|
168 |
|
|
|
169 |
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Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 111MB peak: 114MB)
|
170 |
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|
171 |
|
|
|
172 |
|
|
|
173 |
|
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Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
174 |
|
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|
175 |
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|
176 |
|
|
Available hyper_sources - for debug and ip models
|
177 |
|
|
None Found
|
178 |
|
|
|
179 |
|
|
@N: MT206 |Auto Constrain mode is enabled
|
180 |
|
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|
181 |
|
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Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
182 |
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|
183 |
9 |
liubenoff |
@N:"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":77:4:77:5|Found counter in view:work.DisplayDriverWrapper(arch) inst symbol_scan_cntr[7:0]
|
184 |
5 |
liubenoff |
|
185 |
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Starting factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
186 |
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|
187 |
|
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|
188 |
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Finished factoring (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
189 |
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|
190 |
|
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|
191 |
|
|
Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
192 |
|
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|
193 |
|
|
|
194 |
|
|
Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
195 |
|
|
|
196 |
|
|
|
197 |
|
|
Starting Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
198 |
|
|
|
199 |
|
|
|
200 |
6 |
liubenoff |
Finished Early Timing Optimization (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
201 |
5 |
liubenoff |
|
202 |
|
|
|
203 |
|
|
Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
204 |
|
|
|
205 |
|
|
|
206 |
|
|
Finished preparing to map (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
207 |
|
|
|
208 |
|
|
|
209 |
|
|
Finished technology mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
210 |
|
|
|
211 |
|
|
Pass CPU time Worst Slack Luts / Registers
|
212 |
|
|
------------------------------------------------------------
|
213 |
6 |
liubenoff |
1 0h:00m:00s -0.76ns 6 / 13
|
214 |
|
|
2 0h:00m:00s -0.76ns 6 / 13
|
215 |
5 |
liubenoff |
|
216 |
6 |
liubenoff |
3 0h:00m:00s -0.62ns 7 / 13
|
217 |
|
|
|
218 |
|
|
|
219 |
|
|
4 0h:00m:00s -0.58ns 6 / 13
|
220 |
|
|
|
221 |
5 |
liubenoff |
Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
222 |
|
|
|
223 |
|
|
@N: FX164 |The option to pack registers in the IOB has not been specified. Please set syn_useioff attribute.
|
224 |
|
|
|
225 |
6 |
liubenoff |
Finished restoring hierarchy (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 140MB peak: 141MB)
|
226 |
5 |
liubenoff |
|
227 |
6 |
liubenoff |
@N: MT611 :|Automatically generated clock DisplayDriverWrapper|bttn_state_derived_clock is not used and is being removed
|
228 |
5 |
liubenoff |
|
229 |
|
|
|
230 |
|
|
@S |Clock Optimization Summary
|
231 |
|
|
|
232 |
|
|
|
233 |
|
|
#### START OF CLOCK OPTIMIZATION REPORT #####[
|
234 |
|
|
|
235 |
6 |
liubenoff |
1 non-gated/non-generated clock tree(s) driving 13 clock pin(s) of sequential element(s)
|
236 |
5 |
liubenoff |
|
237 |
6 |
liubenoff |
8 instances converted, 0 sequential instances remain driven by gated/generated clocks
|
238 |
5 |
liubenoff |
|
239 |
6 |
liubenoff |
=========================== Non-Gated/Non-Generated Clocks ============================
|
240 |
|
|
Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance
|
241 |
|
|
---------------------------------------------------------------------------------------
|
242 |
|
|
@K:CKID0001 clk port 13 bttn_state
|
243 |
|
|
=======================================================================================
|
244 |
5 |
liubenoff |
|
245 |
|
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|
246 |
|
|
##### END OF CLOCK OPTIMIZATION REPORT ######]
|
247 |
|
|
|
248 |
|
|
|
249 |
|
|
Start Writing Netlists (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 107MB peak: 141MB)
|
250 |
|
|
|
251 |
|
|
Writing Analyst data base C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\synwork\impl1_m.srm
|
252 |
|
|
|
253 |
6 |
liubenoff |
Finished Writing Netlist Databases (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 139MB peak: 141MB)
|
254 |
5 |
liubenoff |
|
255 |
|
|
Writing EDIF Netlist and constraint files
|
256 |
|
|
@N: FX1056 |Writing EDF file: C:\Projects\single-14-segment-display-driver-w-decoder\Project\Lattice_FPGA_Build\impl1\impl1.edi
|
257 |
|
|
L-2016.03L-1
|
258 |
|
|
@N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF
|
259 |
|
|
|
260 |
9 |
liubenoff |
Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
261 |
5 |
liubenoff |
|
262 |
|
|
|
263 |
6 |
liubenoff |
Start final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 143MB peak: 145MB)
|
264 |
5 |
liubenoff |
|
265 |
6 |
liubenoff |
@W: MT420 |Found inferred clock DisplayDriverWrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
|
266 |
5 |
liubenoff |
|
267 |
|
|
|
268 |
|
|
##### START OF TIMING REPORT #####[
|
269 |
9 |
liubenoff |
# Timing Report written on Tue Jan 17 23:41:24 2017
|
270 |
5 |
liubenoff |
#
|
271 |
|
|
|
272 |
|
|
|
273 |
|
|
Top view: DisplayDriverWrapper
|
274 |
6 |
liubenoff |
Requested Frequency: 433.9 MHz
|
275 |
5 |
liubenoff |
Wire load mode: top
|
276 |
|
|
Paths requested: 5
|
277 |
|
|
Constraint File(s):
|
278 |
|
|
@N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing.
|
279 |
|
|
|
280 |
|
|
@N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock.
|
281 |
|
|
|
282 |
|
|
|
283 |
|
|
|
284 |
|
|
Performance Summary
|
285 |
|
|
*******************
|
286 |
|
|
|
287 |
|
|
|
288 |
6 |
liubenoff |
Worst slack in design: -0.407
|
289 |
5 |
liubenoff |
|
290 |
6 |
liubenoff |
Requested Estimated Requested Estimated Clock Clock
|
291 |
|
|
Starting Clock Frequency Frequency Period Period Slack Type Group
|
292 |
|
|
----------------------------------------------------------------------------------------------------------------------------------
|
293 |
|
|
DisplayDriverWrapper|clk 433.9 MHz 368.8 MHz 2.305 2.712 -0.407 inferred Autoconstr_clkgroup_0
|
294 |
|
|
==================================================================================================================================
|
295 |
5 |
liubenoff |
|
296 |
|
|
|
297 |
|
|
|
298 |
|
|
|
299 |
|
|
|
300 |
|
|
Clock Relationships
|
301 |
|
|
*******************
|
302 |
|
|
|
303 |
|
|
Clocks | rise to rise | fall to fall | rise to fall | fall to rise
|
304 |
|
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
305 |
|
|
Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack
|
306 |
|
|
-------------------------------------------------------------------------------------------------------------------------------------------
|
307 |
6 |
liubenoff |
DisplayDriverWrapper|clk DisplayDriverWrapper|clk | 2.305 -0.407 | No paths - | No paths - | No paths -
|
308 |
5 |
liubenoff |
===========================================================================================================================================
|
309 |
|
|
Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
|
310 |
|
|
'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.
|
311 |
|
|
|
312 |
|
|
|
313 |
|
|
|
314 |
|
|
Interface Information
|
315 |
|
|
*********************
|
316 |
|
|
|
317 |
|
|
No IO constraint found
|
318 |
|
|
|
319 |
|
|
|
320 |
|
|
|
321 |
|
|
====================================
|
322 |
|
|
Detailed Report for Clock: DisplayDriverWrapper|clk
|
323 |
|
|
====================================
|
324 |
|
|
|
325 |
|
|
|
326 |
|
|
|
327 |
|
|
Starting Points with Worst Slack
|
328 |
|
|
********************************
|
329 |
|
|
|
330 |
6 |
liubenoff |
Starting Arrival
|
331 |
|
|
Instance Reference Type Pin Net Time Slack
|
332 |
|
|
Clock
|
333 |
|
|
-------------------------------------------------------------------------------------------------------------------
|
334 |
|
|
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[0] 0.933 -0.407
|
335 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[1] 0.933 -0.348
|
336 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[2] 0.933 -0.348
|
337 |
|
|
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[3] 0.933 -0.289
|
338 |
|
|
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[4] 0.933 -0.289
|
339 |
|
|
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[5] 0.933 -0.230
|
340 |
|
|
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX Q symbol_scan_cntr[6] 0.933 -0.230
|
341 |
|
|
bttn_state_fifo[3] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[3] 0.798 0.123
|
342 |
|
|
bttn_state DisplayDriverWrapper|clk FD1S3AX Q bttn_state_i 0.753 0.168
|
343 |
|
|
bttn_state_fifo[1] DisplayDriverWrapper|clk FD1S3JX Q bttn_state_fifo[1] 0.838 0.606
|
344 |
|
|
===================================================================================================================
|
345 |
5 |
liubenoff |
|
346 |
|
|
|
347 |
|
|
Ending Points with Worst Slack
|
348 |
|
|
******************************
|
349 |
|
|
|
350 |
6 |
liubenoff |
Starting Required
|
351 |
|
|
Instance Reference Type Pin Net Time Slack
|
352 |
|
|
Clock
|
353 |
|
|
--------------------------------------------------------------------------------------------------------------------------------
|
354 |
|
|
symbol_scan_cntr[7] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[7] 2.094 -0.407
|
355 |
|
|
symbol_scan_cntr[5] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[5] 2.094 -0.348
|
356 |
|
|
symbol_scan_cntr[6] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[6] 2.094 -0.348
|
357 |
|
|
symbol_scan_cntr[3] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[3] 2.094 -0.289
|
358 |
|
|
symbol_scan_cntr[4] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[4] 2.094 -0.289
|
359 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[1] 2.094 -0.230
|
360 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX D symbol_scan_cntr_s[2] 2.094 -0.230
|
361 |
|
|
symbol_scan_cntr[0] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
362 |
|
|
symbol_scan_cntr[1] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
363 |
|
|
symbol_scan_cntr[2] DisplayDriverWrapper|clk FD1P3DX SP bttn_state_fifo_0io_RNIB9K02[0] 2.122 0.123
|
364 |
|
|
================================================================================================================================
|
365 |
5 |
liubenoff |
|
366 |
|
|
|
367 |
|
|
|
368 |
|
|
Worst Path Information
|
369 |
|
|
***********************
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
Path information for path number 1:
|
373 |
6 |
liubenoff |
Requested Period: 2.305
|
374 |
|
|
- Setup time: 0.211
|
375 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
376 |
6 |
liubenoff |
= Required time: 2.094
|
377 |
5 |
liubenoff |
|
378 |
6 |
liubenoff |
- Propagation time: 2.501
|
379 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
380 |
6 |
liubenoff |
= Slack (critical) : -0.407
|
381 |
5 |
liubenoff |
|
382 |
6 |
liubenoff |
Number of logic level(s): 5
|
383 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
384 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
385 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
386 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
387 |
|
|
|
388 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
389 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
390 |
|
|
-------------------------------------------------------------------------------------------
|
391 |
|
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
392 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
393 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
394 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
395 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
396 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
397 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
398 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
399 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
400 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
401 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
402 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
403 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.894 -
|
404 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
405 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.894 -
|
406 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.501 -
|
407 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
408 |
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.501 -
|
409 |
|
|
===========================================================================================
|
410 |
5 |
liubenoff |
|
411 |
|
|
|
412 |
|
|
Path information for path number 2:
|
413 |
6 |
liubenoff |
Requested Period: 2.305
|
414 |
|
|
- Setup time: 0.211
|
415 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
416 |
6 |
liubenoff |
= Required time: 2.094
|
417 |
5 |
liubenoff |
|
418 |
6 |
liubenoff |
- Propagation time: 2.442
|
419 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
420 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
421 |
5 |
liubenoff |
|
422 |
6 |
liubenoff |
Number of logic level(s): 4
|
423 |
|
|
Starting point: symbol_scan_cntr[1] / Q
|
424 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
425 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
426 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
427 |
|
|
|
428 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
429 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
430 |
|
|
-------------------------------------------------------------------------------------------
|
431 |
|
|
symbol_scan_cntr[1] FD1P3DX Q Out 0.933 0.933 -
|
432 |
|
|
symbol_scan_cntr[1] Net - - - - 15
|
433 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A0 In 0.000 0.933 -
|
434 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
435 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
436 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
437 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
438 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
439 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
440 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
441 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
442 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
443 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
444 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
445 |
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
446 |
|
|
===========================================================================================
|
447 |
5 |
liubenoff |
|
448 |
|
|
|
449 |
|
|
Path information for path number 3:
|
450 |
6 |
liubenoff |
Requested Period: 2.305
|
451 |
|
|
- Setup time: 0.211
|
452 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
453 |
6 |
liubenoff |
= Required time: 2.094
|
454 |
5 |
liubenoff |
|
455 |
6 |
liubenoff |
- Propagation time: 2.442
|
456 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
457 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
458 |
5 |
liubenoff |
|
459 |
6 |
liubenoff |
Number of logic level(s): 4
|
460 |
|
|
Starting point: symbol_scan_cntr[2] / Q
|
461 |
|
|
Ending point: symbol_scan_cntr[7] / D
|
462 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
463 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
464 |
|
|
|
465 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
466 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
467 |
|
|
-------------------------------------------------------------------------------------------
|
468 |
|
|
symbol_scan_cntr[2] FD1P3DX Q Out 0.933 0.933 -
|
469 |
|
|
symbol_scan_cntr[2] Net - - - - 15
|
470 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C A1 In 0.000 0.933 -
|
471 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.784 1.717 -
|
472 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
473 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.717 -
|
474 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.776 -
|
475 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
476 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.776 -
|
477 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C COUT Out 0.059 1.835 -
|
478 |
|
|
symbol_scan_cntr_cry[6] Net - - - - 1
|
479 |
|
|
symbol_scan_cntr_s_0[7] CCU2C CIN In 0.000 1.835 -
|
480 |
|
|
symbol_scan_cntr_s_0[7] CCU2C S0 Out 0.607 2.442 -
|
481 |
|
|
symbol_scan_cntr_s[7] Net - - - - 1
|
482 |
|
|
symbol_scan_cntr[7] FD1P3DX D In 0.000 2.442 -
|
483 |
|
|
===========================================================================================
|
484 |
5 |
liubenoff |
|
485 |
|
|
|
486 |
|
|
Path information for path number 4:
|
487 |
6 |
liubenoff |
Requested Period: 2.305
|
488 |
|
|
- Setup time: 0.211
|
489 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
490 |
6 |
liubenoff |
= Required time: 2.094
|
491 |
5 |
liubenoff |
|
492 |
6 |
liubenoff |
- Propagation time: 2.442
|
493 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
494 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
495 |
5 |
liubenoff |
|
496 |
6 |
liubenoff |
Number of logic level(s): 4
|
497 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
498 |
|
|
Ending point: symbol_scan_cntr[5] / D
|
499 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
500 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
501 |
|
|
|
502 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
503 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
504 |
|
|
-------------------------------------------------------------------------------------------
|
505 |
|
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
506 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
507 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
508 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
509 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
510 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
511 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
512 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
513 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
514 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
515 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
516 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
517 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S0 Out 0.607 2.442 -
|
518 |
|
|
symbol_scan_cntr_s[5] Net - - - - 1
|
519 |
|
|
symbol_scan_cntr[5] FD1P3DX D In 0.000 2.442 -
|
520 |
|
|
===========================================================================================
|
521 |
5 |
liubenoff |
|
522 |
|
|
|
523 |
|
|
Path information for path number 5:
|
524 |
6 |
liubenoff |
Requested Period: 2.305
|
525 |
|
|
- Setup time: 0.211
|
526 |
5 |
liubenoff |
+ Clock delay at ending point: 0.000 (ideal)
|
527 |
6 |
liubenoff |
= Required time: 2.094
|
528 |
5 |
liubenoff |
|
529 |
6 |
liubenoff |
- Propagation time: 2.442
|
530 |
5 |
liubenoff |
- Clock delay at starting point: 0.000 (ideal)
|
531 |
6 |
liubenoff |
= Slack (non-critical) : -0.348
|
532 |
5 |
liubenoff |
|
533 |
6 |
liubenoff |
Number of logic level(s): 4
|
534 |
|
|
Starting point: symbol_scan_cntr[0] / Q
|
535 |
|
|
Ending point: symbol_scan_cntr[6] / D
|
536 |
5 |
liubenoff |
The start point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
537 |
|
|
The end point is clocked by DisplayDriverWrapper|clk [rising] on pin CK
|
538 |
|
|
|
539 |
6 |
liubenoff |
Instance / Net Pin Pin Arrival No. of
|
540 |
|
|
Name Type Name Dir Delay Time Fan Out(s)
|
541 |
|
|
-------------------------------------------------------------------------------------------
|
542 |
|
|
symbol_scan_cntr[0] FD1P3DX Q Out 0.933 0.933 -
|
543 |
|
|
symbol_scan_cntr[0] Net - - - - 15
|
544 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C A1 In 0.000 0.933 -
|
545 |
|
|
symbol_scan_cntr_cry_0[0] CCU2C COUT Out 0.784 1.717 -
|
546 |
|
|
symbol_scan_cntr_cry[0] Net - - - - 1
|
547 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C CIN In 0.000 1.717 -
|
548 |
|
|
symbol_scan_cntr_cry_0[1] CCU2C COUT Out 0.059 1.776 -
|
549 |
|
|
symbol_scan_cntr_cry[2] Net - - - - 1
|
550 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C CIN In 0.000 1.776 -
|
551 |
|
|
symbol_scan_cntr_cry_0[3] CCU2C COUT Out 0.059 1.835 -
|
552 |
|
|
symbol_scan_cntr_cry[4] Net - - - - 1
|
553 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C CIN In 0.000 1.835 -
|
554 |
|
|
symbol_scan_cntr_cry_0[5] CCU2C S1 Out 0.607 2.442 -
|
555 |
|
|
symbol_scan_cntr_s[6] Net - - - - 1
|
556 |
|
|
symbol_scan_cntr[6] FD1P3DX D In 0.000 2.442 -
|
557 |
|
|
===========================================================================================
|
558 |
5 |
liubenoff |
|
559 |
|
|
|
560 |
|
|
|
561 |
|
|
##### END OF TIMING REPORT #####]
|
562 |
|
|
|
563 |
|
|
Constraints that could not be applied
|
564 |
|
|
None
|
565 |
|
|
|
566 |
6 |
liubenoff |
Finished final timing analysis (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
567 |
5 |
liubenoff |
|
568 |
|
|
|
569 |
6 |
liubenoff |
Finished timing report (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 144MB peak: 145MB)
|
570 |
5 |
liubenoff |
|
571 |
|
|
---------------------------------------
|
572 |
|
|
Resource Usage Report
|
573 |
6 |
liubenoff |
Part: lfe5um5g_45f-8
|
574 |
5 |
liubenoff |
|
575 |
6 |
liubenoff |
Register bits: 13 of 43848 (0%)
|
576 |
5 |
liubenoff |
PIC Latch: 0
|
577 |
6 |
liubenoff |
I/O cells: 19
|
578 |
5 |
liubenoff |
|
579 |
|
|
|
580 |
|
|
Details:
|
581 |
6 |
liubenoff |
CCU2C: 5
|
582 |
|
|
FD1P3DX: 8
|
583 |
|
|
FD1S3AX: 1
|
584 |
5 |
liubenoff |
FD1S3JX: 3
|
585 |
|
|
GSR: 1
|
586 |
6 |
liubenoff |
IB: 3
|
587 |
|
|
IFS1P3JX: 1
|
588 |
|
|
INV: 2
|
589 |
|
|
OB: 16
|
590 |
|
|
ORCALUT4: 4
|
591 |
5 |
liubenoff |
PUR: 1
|
592 |
6 |
liubenoff |
ROM128X1A: 14
|
593 |
|
|
VHI: 1
|
594 |
5 |
liubenoff |
VLO: 1
|
595 |
|
|
Mapper successful!
|
596 |
|
|
|
597 |
6 |
liubenoff |
At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 31MB peak: 145MB)
|
598 |
5 |
liubenoff |
|
599 |
|
|
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
|
600 |
9 |
liubenoff |
# Tue Jan 17 23:41:24 2017
|
601 |
5 |
liubenoff |
|
602 |
|
|
###########################################################]
|