URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [message.xml] - Blame information for rev 5

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            71001181
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            51001046
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            button
        
    
    
        
            35002000
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            35921504
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            C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1
        
        
            35921012
            Info
            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(16): 
            displaydriverwdecoder_top
            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd
            16
        
        
            35921010
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            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(50): 
            arch
            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd
            50
        
        
            35921012
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            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15): 
            displaydriverwrapper
            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd
            15
        
        
            35921010
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            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(35): 
            arch
            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd
            35
        
        
            35921205
            Warning
            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(31): 
            DisplayDriverWrapper
            arch
            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd
            31
        
        
            35001611
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            1166052
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            logical
            clk
            clk
        
        
            1166064
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            clk
        
        
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            logical
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            reset
        
        
            1166064
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            reset
        
        
            1166052
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            logical
            button
            button
        
        
            1166064
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            input
            button
        
        
            1163101
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            6
        
    
    
        
            60001135
            Info
        
    
    
        
            1166052
            Warning
            logical
            button
            button
        
        
            1163101
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            1
        
    
    
        
            2011000
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            2019991
            Warning
            CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
            CD638
            C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd
            38
            11
            38
            15
            Signal empty is undriven. Either assign the signal a value or remove the signal declaration.
        
        
            2019991
            Warning
            MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9|Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
            MT529
            c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd
            76
            8
            76
            9
            Found inferred clock DisplayDriverWrapper|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. 
        
        
            2019993
            Warning
            MT420 |Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
            MT420
            Found inferred clock DisplayDriverWrapper|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"
        
    


Line No.	Rev	Author	Line
1	5	liubenoff
2
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5			`71001181`
6			`Warning`
7			`0`
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12			`51001046`
13			`Warning`
14			`button`
15
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19			`35002000`
20			`Info`
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23			`35921504`
24			`Info`
25
26			`C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1`
27
28
29			`35921012`
30			`Info`
31			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(16):`
32			`displaydriverwdecoder_top`
33			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd`
34			`16`
35
36
37			`35921010`
38			`Info`
39			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(50):`
40			`arch`
41			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd`
42			`50`
43
44
45			`35921012`
46			`Info`
47			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15):`
48			`displaydriverwrapper`
49			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd`
50			`15`
51
52
53			`35921010`
54			`Info`
55			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(35):`
56			`arch`
57			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd`
58			`35`
59
60
61			`35921205`
62			`Warning`
63			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(31):`
64			`DisplayDriverWrapper`
65			`arch`
66			`c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd`
67			`31`
68
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70			`35001611`
71			`Warning`
72
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74			`1166052`
75			`Warning`
76			`logical`
77			`clk`
78			`clk`
79
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81			`1166064`
82			`Warning`
83			`input`
84			`clk`
85
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87			`1166052`
88			`Warning`
89			`logical`
90			`reset`
91			`reset`
92
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94			`1166064`
95			`Warning`
96			`input`
97			`reset`
98
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100			`1166052`
101			`Warning`
102			`logical`
103			`button`
104			`button`
105
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107			`1166064`
108			`Warning`
109			`input`
110			`button`
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114			`Warning`
115			`6`
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120			`60001135`
121			`Info`
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126			`1166052`
127			`Warning`
128			`logical`
129			`button`
130			`button`
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133			`1163101`
134			`Warning`
135			`1`
136
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140			`2011000`
141			`Info`
142
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144			`2019991`
145			`Warning`
146			`CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd":38:11:38:15\|Signal empty is undriven. Either assign the signal a value or remove the signal declaration.`
147			`CD638`
148			`C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\DisplayDriverWrapper.vhd`
149			`38`
150			`11`
151			`38`
152			`15`
153			`Signal empty is undriven. Either assign the signal a value or remove the signal declaration.`
154
155
156			`2019991`
157			`Warning`
158			`MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd":76:8:76:9\|Found inferred clock DisplayDriverWrapper\|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.`
159			`MT529`
160			`c:\projects\single-14-segment-display-driver-w-decoder\project\sources\displaydriverwdecoder_top.vhd`
161			`76`
162			`8`
163			`76`
164			`9`
165			`Found inferred clock DisplayDriverWrapper\|clk which controls 8 sequential elements including DDwD_Top.ascii_reg[7:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.`
166
167
168			`2019993`
169			`Warning`
170			`MT420 \|Found inferred clock DisplayDriverWrapper\|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"`
171			`MT420`
172			`Found inferred clock DisplayDriverWrapper\|clk with period 0.82ns. Please declare a user-defined clock on object "p:clk"`
173
174
175

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Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [message.xml] - Blame information for rev 5