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URL https://opencores.org/ocsvn/single-14-segment-display-driver-w-decoder/single-14-segment-display-driver-w-decoder/trunk

Subversion Repositories single-14-segment-display-driver-w-decoder

[/] [single-14-segment-display-driver-w-decoder/] [trunk/] [Project/] [Lattice_FPGA_Build/] [impl1/] [message.xml] - Blame information for rev 9

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            1101672
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            Warning
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            C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf(29): Semantic error in "USERCODE ASCII "G.L." ; ":
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            Invalid Ascii char <.>.Invalid Ascii char <.>.
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            C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf
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            29
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            Warning
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            1 semantic error
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            n_rst_c
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            C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/DisplayDriverwDecoder.lpf
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            C:/Projects/single-14-segment-display-driver-w-decoder/Project/Lattice_FPGA_Build/impl1
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            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(16):
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            displaydriverwdecoder_top
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            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd
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            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwdecoder_top.vhd(50):
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            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(15):
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            displaydriverwrapper
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            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(35):
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            c:/projects/single-14-segment-display-driver-w-decoder/project/sources/displaydriverwrapper.vhd(31):
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            DisplayDriverWrapper
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            logical
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            clk
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            input
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            clk
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            reset
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            symbol_scan_cntr_cry_0_S0[0]
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            logical
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            symbol_scan_cntr_s_0_S1[7]
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            symbol_scan_cntr_s_0_COUT[7]
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            CD638 :"C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd":42:11:42:19|Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
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            C:\Projects\single-14-segment-display-driver-w-decoder\Project\Sources\display_driver_w_decoder.vhd
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            Signal ascii_reg is undriven. Either assign the signal a value or remove the signal declaration.
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            MT529 :"c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd":52:8:52:9|Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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            c:\projects\single-14-segment-display-driver-w-decoder\project\sources\display_driver_wrapper.vhd
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            Found inferred clock display_driver_wrapper|clk which controls 5 sequential elements including bttn_state. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance.
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            MT420 |Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
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            MT420
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            Found inferred clock display_driver_wrapper|clk with period 2.30ns. Please declare a user-defined clock on object "p:clk"
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